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| 型號： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁數(shù)： | 28/160頁 |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
28
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Table 10
CAN Special Function Registers
SFR
ACCESS
PELICAN
REG.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SFR
ADDR
CANADR
Read/
Write
Read/
Write
Read/
Write
Read
Write
-
CANA7 CANA6 CANA5 CANA4 CANA3 CANA2 CANA1 CANA0
C1
CANDAT
-
CAND7 CAND6 CAND5 CAND4 CAND3 CAND2 CAND1 CAND0
C2
CANMOD
Mode
TM
RIPM
RPM
SM
STM
LOM
RM
C4
CANSTA
Status
Interrupt
Enable
Interrupt
Command
BS
BEIE
ES
ALIE
TS
EPIE
RS
WUIE
TCS
DOIE
TBS
EIE
DOS
TIE
RBS
RIE
C0
CANCON
Read
Write
BEI
-
ALI
-
EPI
-
WUI
SRR
DOI
CDO
EI
TI
AT
RI
TR
C3
RRB
12.3.2
CANADR
This read/write register defines the address of one of the
PeliCAN internal registers to be accessed via CANDAT. It
could be interpreted as a pointer to the PeliCAN.
The read and write access to the PeliCAN Block register is
performed using the CANDAT register.
With the implemented auto address increment mode a fast
stack-like reading and writing of CAN controller internal
registers is provided. If the currently defined address
within CANADR is above or equal to 32 decimal, the
contentofCANADRisincrementedautomaticallyafterany
read or write access to CANDAT. For instance, loading a
message into the Transmit Buffer can be done by writing
the first Transmit Buffer Address (112 decimal) into
CANADR and then moving byte by byte of the message to
CANDAT. Incrementing CANADR beyond FFh resets
CANADR to 00h.
In case CANADR is below 32 decimal, there is no
automatic address incrementation performed. CANADR
keeps its value even if CANDAT is accessed for reading or
writing. This is to allow polling of registers in the lower
address space of the PeliCAN controller.
12.3.3
CANDAT R
EGISTER
CANDAT is implemented as a read/write register.
The Special Function Register CANDAT appears as a port
to the CAN controller’s internal register (memory location)
being selected by CANADR. Reading or writing CANDAT
is effectively an access to that PeliCAN internal register,
which is selected by CANADR. CANDAT is implemented
as a read/write register.
Note that any access to this register automatically
increments CANADR if the current address within
CANADR is above or equal to 32 decimal.
12.3.4
CANMOD
With a read or write access to CANMOD the Mode
Register of the PeliCAN is accessed directly. The Mode
register is located at address 00h within the PeliCAN
Block.
12.3.5
CANSTA
The CANSTA SFR provides a direct access to the Status
Register of the PeliCAN as well as to the Interrupt Enable
Register, depending on the direction of the access.
Reading CANSTA is an access to the Status Register of
the PeliCAN (address 2). When writing to CANSTA the
Interrupt Enable Register is accessed (address 4).
12.3.6
CANCON
The CANCON SFR provides a direct access to the
Interrupt Register of the PeliCAN as well as to the
Command register, depending on the direction of the
access.
When reading CANCON the Interrupt Register of the
PeliCAN is accessed (address 3), while writing to
CANCON means an access to the Command Register
(address 1).
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