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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 66/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
66
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
14.4
More about UART Modes
More About Mode 0
Serial data enters and exits through RxD. TxD outputs the
shiftclock.8bitsare transmitted/received: 8databits(LSB
first). The baud rate is fixed a
1
6
the oscillator frequency.
Figure 25 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing.
Transmission is initiated by any instruction that uses
S0BUF as a destination register. The “write to S0BUF”
signal at S6P2 also loads a 1 into the 9
th
position of the
transmit shift register and tells the TX Control block to
commence a transmission. The internal timing is such that
one full machine cycle will elapse between “write to
S0BUF” and activation of SEND.
SEND enables the output of the shift register to the
alternate output function line of P3.0 and also enable
SHIFT CLOCK to the alternate output function line of P3.1.
SHIFT CLOCK is low during S3, S4, and S5 of every
machine cycle, and high during S6, S1 and S2. At S6P2 of
every machine cycle in which SEND is active, the contents
of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the
left. When the MSB of the data byte is at the output
position of the shift register, then the 1 that was initially
loaded into the 9
th
position, is just to the left of the MSB,
and all positions to the left of that contain zeros. This
condition flags the TX Control block to do one last shift and
then deactivate SEND and set T1. Both of these actions
occur at S1P1 of the 10
th
machine cycle after “write to
S0BUF”.
Reception is initiated by the condition REN = 1 and
R1 = 0. At S6P2 of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register,
and in the next clock phase activates RECEIVE.
RECEIVE enable SHIFT CLOCK to the alternate output
function line of P3.1. SHIFT CLOCK makes transitions at
S3P1 and S6P1 of every machine cycle. At S6P2 of every
machine cycle. At S6P2 of every machine cycle in which
RECEIVE is active, the contents of the receive shift
register are shifted to the left one position. The value that
comes in from the right is the value that was sampled at
the P3.0 pin at S5P2 of the same machine cycle.
As data bits come in from the right, 1s shift out to the left.
When the 0 that was initially loaded into the weightiness
position arrives at the left most position in the shift register,
it flags the RX Control block to do one last shift and load
S0BUF. At S1P1 of the 10
th
machine cycle after the write
to SCON that cleared RI, RECEIVE is cleared as RI is set.
More About Mode 1
Ten bits are transmitted (through TxD), or received
(through RxD): a start bit (0), 8 data bits (LSB first), and a
stop bit (1). On receive, the stop bit goes into RB8 in
SCON. In the 80C51 the baud rate is determined by the
Timer 1 overflow rate.
Figure 25 shows a simplified functional diagram of the
serial port in Mode1, and associated timings for transmit
receive.
Transmission is initiated by any instruction that uses
S0BUF as a destination register. The “write to S0BUF”
signal also loads a1 into the 9
th
bit position of the transmit
shift register and flags the TX Control unit that a
transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the
next rollover in the divide-by-16 counter. (Thus, the bit
times are synchronized to the divide-by-16 counter, not to
the “write to S0BUF” signal.)
The transmission begins with activation of SEND which
puts the start bit at TxD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift
register to TxD. The first shift pulse occurs one bit time
after that.
As data bits shift out to the right, zeros are clocked in from
the left. When the MSB of the data byte is at the output
position of the shift register, then the 1 that was initially
loaded into the 9
th
position is just to the left of the MSB,
and all positions to the left of that contain zeros. The
condition flags the TX Control unit to do one last shift and
then deactivate SEND and set TI. This occurs at the 10
th
divide-by-16 rollover after “write to S0BUF”.
Reception is initiated by a detected 1-to-0 transition at
RxD. For this purpose RxD is sampled at a rate of 16 times
whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is
immediately reset, and 1 FFH is written into the input shift
register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16
ths
.
At the 7
th
, 8
th
, and 9
th
counter states of each bit time, the
bit detector samples the value of RxD. The value accepted
is the value that was seen in at least 2 of the 3 samples.
This is done for noise rejection. If the value accepted
during the first bit time is not 0, the receive circuits are
reset and the unit goes back to looking for another 1-to-0
transition. This is to provide rejection of false start bits. If
the start bit proves valid, it shifted into the input shift
register, and reception of the rest of the frame will proceed.
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