參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 42/160頁
文件大?。?/td> 601K
代理商: P8XC591
2000 Jul 26
42
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.10 RX M
ESSAGE
C
OUNTER
(RMC)
The RMC Register (CAN Address 9) reflects the number of messages available within the RXFIFO. The value is
incremented with each receive event and decremented by the Release Receive Buffer command. After any reset event,
this register is cleared.
Table 22
RX Message Counter (RMC) (CAN address 9)
7
6
5
4
3
2
1
0
RMC.7
RMC.6
RMC.5
RMC.4
RMC.3
RMC.2
RMC.1
RMC.0
12.5.11 RX B
UFFER
S
TART
A
DDRESS
(RBSA)
TheRBSAregister(CANAddress10)reflectsthecurrently
valid internal RAM address, where the first byte of the
received message, which is mapped to the Receive Buffer
Window, is stored. With the help of this information it is
possible to interpret the internal RAM contents. The
internal RAM address area begins at CAN address 32 and
may be accessed by the CPU for reading and writing
(writing in Reset Mode only).
Example:
If RBSA is set to 24 (decimal), the current message visible
in the Receive Buffer Window (CAN Address 96 -108) is
stored within the internal RAM beginning at RAM address
24. Because the RAM is also mapped directly to the CAN
address space beginning at CAN address 128 (equal to
RAM address 0) this message may also be accessed
using CAN address 152 and the following bytes
(CAN Address = RBSA + 128--> 24 + 128= 152).
Always, the Release Receive Buffer Command is given
while there is at least one more message available within
the FIFO, RBSA is updated to the beginning of the next
message.
On Hardware Reset, this pointer is initialised to “00h”.
Upon a Software Reset (setting of Reset Mode) this
pointer keeps its old value, but the FIFO is cleared, what
means, that the RAM contents are not changed, but the
next received (or transmitted) message will override the
currently visible message within the Receive Buffer
Window.
The RX Buffer Start Address Register appears to the CPU
as a read only memory in Operating Mode and as read /
write memory in Reset Mode.
Table 23
RX Buffer Start Address (RBSA) (CAN address 10)
7
6
5
4
3
2
1
0
RBSA.7
RBSA.6
RBSA.5
RBSA.4
RBSA.3
RBSA.2
RBSA.1
RBSA.0
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