參數(shù)資料
型號(hào): P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁(yè)數(shù): 9/160頁(yè)
文件大?。?/td> 601K
代理商: P8XC591
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2000 Jul 26
9
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
6.2
Pin description
Table 1
Pin description for QFP44/PLCC44, see Note 1.
SYMBOL
PIN
DESCRIPTION
QFP44
PLCC44
RST
4
10
Reset:
A Input to reset the P8xC591. It also provides a reset pulse as output
when Timer T3 overflows.
Port 3 (P3.0 to P3.7)
: 8-bit programmable I/O port lines; Port 3 can
sink/source 4 LSTTL inputs.
P3.0to P3.7
Port 3 pins serve alternate functions as follows:
RXD
: Serial input port for UART;
T2:
T2 event input
TXD
: Serial output port for UART;
RT2:
T2 timer reset signal. Rising edge triggered.
INT0
: External interrupt input 0;
CMSR0:
Compare and Set/Reset output for Timer T2.
INT1
: External interrupt input 1;
CMSR1:
Compare and Set/Reset output for Timer T2.
T0
: Timer 0 external interrupt input;
CMSR2:
Compare and Set/Reset output for Timer T2.
T1
: Timer 1 external interrupt input;
CMSR3:
Compare and Set/Reset output for Timer T2.
WR
: External Data Memory Write strobe;
RD
: External Data Memory Read strobe.
P3.0/RXD
5
11
P3.1/TXD
7
13
P3.2/INT0/CMSR0 8
14
P3.3/INT1/
CMSR1
9
15
P3.4/T0/CMSR2
10
16
P3.5/T1/CMSR3
11
17
P3.6/WR
P3.7/RD
12
13
18
19
During reset, Port 3 will be asynchronously driven resistive HIGH.
Port 3 has four modes selected on a per bit basis by writing to the P3M1 and
P3M2 registers as follows:
P3M1.x
0
0
1
1
1
Open drain
Crystal pin 2:
output of the inverting amplifier that forms the oscillator. Left
open-circuit when an external oscillator clock is used.
Crystal pin 1:
input to the inverting amplifier that forms the oscillator, and
input to the internal clock generator. Receives the external oscillator clock
signal when an external oscillator is used.
Ground;
circuit ground potential.
Power supply;
power supply pin during normal operation and power
reduction modes.
P3M2.x
0
1
0
Mode Description
Pseudo-bidirectional (standard c51 configuration default)
Push-Pull
High impedance
XTAL2
14
20
XTAL1
15
21
V
SS
V
DD
16
17
22
23
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