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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 102/160頁(yè) |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
102
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.3.4
M
ASTER
T
RANSMITTER AND
M
ASTER
R
ECEIVER
M
ODES
The master mode is entered in the main program. To enter
the master transmitter mode, the main program must first
load the internal data RAM with the slave address, data
bytes, and the number of data bytes to be transmitted. To
enter the master receiver mode, the main program must
first load the internal data RAM with the slave address and
the number of data bytes to be received. The R/W bit
determines whether SIO1 operates in the master
transmitter or master receiver mode.
Master mode operation commences when the STA bit in
S1CION is set by the SETB instruction and data transfer is
controlled by the master state service routines in
accordance with Table 61, Table 62, Figure 37 and
Figure 38. In the example below, 4 bytes are transferred.
There is no repeated START condition. In the event of lost
arbitration, the transfer is restarted when the bus becomes
free.Ifabuserroroccurs,theI
2
CbusisreleasedandSIO1
enters the not selected slave receiver mode. If a slave
device returns a not acknowledge, a STOP condition is
generated.
A repeated START condition can be included in the serial
transfer if the STA flag is set instead of the STO flag in the
state service routines vectored to by status codes 28H and
58H. Additional software must be written to determine
which data is transferred after a repeated START
condition.
15.3.5
S
LAVE
T
RANSMITTER AND
S
LAVE
R
ECEIVER
M
ODES
After initialization, SIO1 continually tests the I
2
C bus and
branches to one of the slave state service routines if it
detects its own slave address or the general call address
(see Table 63, Table 64, Figure 39, and Figure 40). If
arbitration was lost while in the master mode, the master
mode is restarted after the current transfer. If a bus error
occurs, the I
2
C bus is released and SIO1 enters the not
selected slave receiver mode.
In the slave receiver mode, a maximum of 8 received data
bytes can be stored in the internal data RAM. A maximum
of 8 bytes ensures that other RAM locations are not
overwritten if a master sends more bytes. If more than 8
bytes are transmitted, a not acknowledge is returned, and
SIO1 enters the not addressed slave receiver mode. A
maximum of one received data byte can be stored in the
internal data RAM after a general call address is detected.
If more than one byte is transmitted, a not acknowledge is
returnedandSIO1entersthenotaddressedslavereceiver
mode.
In the slave transmitter mode, data to be transmitted is
obtained from the same locations in the internal data RAM
that were previously loaded by the main program. After a
not acknowledge has been returned by a master receiver
device, SIO1 enters the not addressed slave mode.
15.3.6
A
DAPTING
T
HE
S
OFTWARE
F
OR
D
IFFERENT
A
PPLICATIONS
The following software example shows the typical
structure of the interrupt routine including the 26 state
service routines and may be used as a base for user
applications.Ifoneormoreofthefourmodesarenotused,
the associated state service routines may be removed but,
care should be taken that a deleted routine can never be
invoked.
This example does not include any time-out routines. In
the slave modes, time-out routines are not very useful
since, in these modes, SIO1 behaves essentially as a
passivedevice.Inthemastermodes,aninternaltimermay
be used to cause a time-out if a serial transfer is not
complete after a defined period of time. This time period is
defined by the system connected to the I
2
C bus.
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