參數(shù)資料
型號(hào)： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁(yè)數(shù)： 61/160頁(yè)
文件大?。?/td> 601K
代理商： P8XC591
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2000 Jul 26
61
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
14.3
Baud Rate Generation
There are several possibilities to generate the baud rate
clock for the serial port depending on the mode in which it
is operating.
For clarification some terms regarding the difference
between “baud rate clock” and “baud rate” should be
mentioned. The serial interface requires a clock rate which
is 16 times the baud rate for internal synchronization.
Therefore, the baud rate generators have to provide a
“baud rate clock” to the serial interface which - there
divided by 16 - results in the actual “baud rate”. However,
all formulas given in the following section already include
the factor and calculate the final baud rate. Further, the
abbreviation f
CLK
refers to the external clock frequency
(oscillator or external input clock operation).
The baud rate of the serial port is controlled by the two bits
SPS and SMOD1 which are located in the Special
Function Registers S0PSH and PCON. In SFRs S0PSH
and S0PSL the prescaler load value of the internal baud
rate generator can be programmed (see Table 38 to 43).
14.3.1
Table 38
Internal Baud Rate Generator Prescaler Low Register S0PSL (address FAH)
Prescaler load value
I
NTERNAL
B
AUD
R
ATE
G
ENERATOR
P
RESCALER
S0PSH, S0PSL
Table 39
Description of S0PSL bits
Table 40
Internal Baud Rate Generator Prescaler High Register S0PSH (address FBH)
Prescaler higher nibble load value
Table 41
Description of S0PSH bits
14.3.2
Table 42
PCON (address 87H)
Prescaler load value
PCON
FOR THE
I
NTERNAL
B
AUD
R
ATE
G
ENERATOR
Table 43
Description of SMOD1 and SMOD0 bits
7
6
5
4
3
2
1
0
prescaler load value
BIT
7 to 0
SYMBOL
DESCRIPTION
Baud reload low value.
Lower 8 bits of the baud rate timer reload value.
7
6
5
4
3
2
1
0
SPS
higher nibble load value
BIT
7
SYMBOL
SPS
DESCRIPTION
Baud rate generator enable.
When set, the baud rate of serial interface is derived from
the dedicated baud rate generator. When cleared (default after reset), baud rate is derived
from the Timer 1 overflow rate.
Reserved.
Baud rate generator reload high value.
Upper four bits of the baud rate timer value.
6 to 4
3 to 0
7
6
5
4
3
2
1
0
SMOD1
SMOD0
(POF)
(WLE)
(GF1)
(GF0)
(PD)
(IDL)
BIT
7
SYMBOL
SMOD1
DESCRIPTION
Double Baud rate.
When set, the baud rate of serial interface is modes 1, 2, 3 is
doubled. After reset this bit is cleared.
Double Baud rate.
Selects SM0/FE for SCON.7 bit.
(POF) to (IDL) Description refer to Section 11.3.5 “Power Control Register (PCON)”.
6
SMOD0
5 to 0
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