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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 82/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
82
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
15.2.12.1 ENS1, the SIO1 enable bit
ENS1 = “0”: When ENS1 is “0”, the SDA and SCL input
signals are ignored, SIO1 is in the not addressed slave
state, and the STO bit in S1CON is forced to 0. No other
bits are affected.
ENS1 = “1”: When ENS1 is 1, I
2
C is enabled. Note, that
P1.6andP1.7havetosettoOpenDrainbywritingthePort
mode registers P1M1.x and P1M2.x bits 6 and 7 with a 1
(see Section 6.2 “Pin description”).
ENS1shouldnotbeusedtotemporarilyreleaseSIO1from
the I
2
C bus since, when ENS1 is reset, the I
2
C bus status
is lost. The AA flag should be used instead (see
description of the AA flag in the following text).
In the following text, it is assumed that ENS1 = 1.
15.2.12.2 STA, the START flag
STA = “1”: When the STA bit is set to enter a master mode,
the SIO1 hardware checks the status of the I
2
C bus and
generates a START condition if the bus is free. If the bus
is not free, then SIO1 waits for a STOP condition (which
will free the bus) and generates a START condition after a
delay of a half clock period of the internal serial clock
generator.
If STA is set while SIO1 is already in a master mode and
one or more bytes are transmitted or received, SIO1
transmits a repeated START condition. STA may be set at
any time. STA may also be set when SIO1 is an addressed
slave.
STA = “0”: When the STA bit is reset, no START condition
or repeated START condition will be generated.
15.2.12.3 STO, the STOP Flag
STO = “1”: When the STO bit is set while SIO1 is in a
master mode, a STOP condition is transmitted to the I
2
C
bus. When the STOP condition is detected on the bus, the
SIO1 hardware clears the STO flag. In a slave mode, the
STO flag may be set to recover from an error condition. In
this case, no STOP condition is transmitted to the I
2
C bus.
However, the SIO1 hardware behaves as if a STOP
condition has been received and switches to the defined
not addressed slave receiver mode. The STO flag is
automatically cleared by hardware.
If the STA and STO bits are both set, the a STOP condition
is transmitted to the I
2
C bus if SIO1 is in a master mode (in
a slave mode, SIO1 generates an internal STOP condition
which is not transmitted). SIO1 then transmits a START
condition.
STO = “0”: When the STO bit is reset, no STOP condition
will be generated.
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