- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369945 > P8XC591 (NXP Semiconductors N.V.) HiRel FPGA, Low-Power 1.0?? CMOS Technology PDF資料下載
參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 64/160頁(yè) |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)當(dāng)前第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)
2000 Jul 26
64
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
With the baud rate generator as clock source for the serial
port in Mode 1 and Mode 3, the baud rate of can be
determined as follows:
Mode 1, 3 baud rate =
Baud rate generator overflow rate =
2
12
- S0PS with S0PS = S0PSH.3 - 0, S0PSL.7 - 0.
S0PS: Baud Rate Generator Prescaler load value
Table 47 lists baud rates and how they can be obtained
from the Internal Baud Rate Generator.
14.3.8
U
SING
T
IMER
1
TO
G
ENERATE
B
AUD
R
ATES
In Mode 1 and 3 of the serial port also timer 1 can be used
for generating baud rates. Then the baud rate is
determined by the timer 1 overflow rate and the value of
SMOD1 as follows:
SMOD1
(baud rate generator overflow rate)
osciillator frequency
×
32
×
-----------2
TheTimer 1interruptisusuallydisabledinthisapplication.
Timer 1 itself can be configured for either “timer” or
“counter” operation, and in any of its operating modes. In
most typical applications, it is configured for “timer”
operation in the auto-reload (high nibble of TMOD =
0010B). In this case the baud rate is given by the formula:
Very low baud rates can be achieved with Timer 1 if
leavingtheTimer 1interruptenabled,configuringthetimer
to run as 16-bit timer (high nibble of TMOD = 0001B), and
using the Timer 1 interrupt for a 16-bit software reload.
Table 49 lists lower baud rates and how they can be
obtained from Timer 1.
Mode 1, 3 baud rate
SMOD1
32
2
(timer 1 overflow rate)
×
=
Mode1 3 baud rate =2
SMOD1
256
TH1
(
–
(
×
6
32
)
)
×
--------------------------oscillator frequency
Table 44
Serial Port Control Register SCON (address)
Table 45
Description of S0PSH and S0PSL bits
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
BIT
SYMBOL
DESCRIPTION
7
6
5
SM0
SM1
SM2
See Table 46.
See Table 46.
Enables the multiprocessor communication feature in Modes 2 and 3.
In Mode 2 or
3, if SM2 is set to 1, then RI will not be activated if the received 9
th
data bit (RB8) is 0. In
Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In
Mode 0, SM2 should be 0.
Enables serial reception.
Set by software to enable reception. Clear by software to
disable reception.
The 9
th
data bit that will be transmitted in Modes 2 and 3.
Set or clear by software as
desired.
In Modes 2 and 3, is the 9
th
data bit that was received.
In Mode 1, if SM2 = 0, RB8 is
the stop bit that was received. In Mode 0, RB8 is not used.
Transmit interrupt flag.
Set by hardware at the end of the 8
th
bit time in Mode 0, or at
the beginning of the stop bit in the other modes, in any serial transmission. Must be
cleared by software.
Receive interrupt flag.
Set by hardware at the end of the 8
th
bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
4
REN
3
TB8
2
RB8
1
TI
0
RI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P90CE201 | 16-bit microcontroller |
| P90CE201AEB | 16-bit microcontroller |
| P9217 | PbS photoconductive detector |
| P930 | CdS photoconductive cell |
| PA025XSB | This technical specification applies to 2.5inch color TFT-LCD panel. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P8XC592 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCE598 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontroller with on-chip CAN |
| P8XCL580HFH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8XCL580HFT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage 8-bit microcontrollers with UART, I2C-bus and ADC |
| P8Z77 DELUXE | 制造商:Asus 功能描述:P8Z77-V Deluxe ATX Motherboard |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。