參數(shù)資料
型號: P8XC591
廠商: NXP Semiconductors N.V.
英文描述: HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述: 單芯片8 - CAN控制器位微控制器
文件頁數(shù): 19/160頁
文件大?。?/td> 601K
代理商: P8XC591
2000 Jul 26
19
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Fig.7 Dual DPTR:
handbook, full pagewidth
DPH
(83H)
BT0
AUXR1
DPS
DPL
(82H)
EXTERNAL
DATA
MEMORY
DPTR0
MHI007
DPTR1
7.4
Dual DPTR
The dual DPTR structure (see Figure 7) is a way by which
the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that
address the external memory, and a single bit called DPS
= AUXR1/bit0 that allows the program code to switch
between them.
The DPS bit status should be saved by software when
switching between DPTR0 and DPTR1.
Note that bit 2 is not writable and is always read as a zero.
This allows the DPS bit to be quickly toggled simply by
executing an INC AUXR1 instruction without affecting the
other bits.
DPTR Instructions
TheinstructionsthatrefertoDPTRrefertothedatapointer
that is currently selected using the AUXR1/bit 0 register.
The six instructions that use the DPTR are as follows:
INC DPTRIncrements the data pointer by 1
MCV DPTR, #data 16
constant
MOV A, @ A+DPTR
Loads the DPTR with a 16-bit
Move code byte relative to
DPTR to ACC
Move external RAM (16-bit
address) to ACC
Move ACC to external RAM
(16-bit address)
Jump indirect relative to
DPTR
MOVX A, @ DPTR
MOVX @ DPTR, A
JMP @ A + DPTR
The data pointer can be accessed on a byte-by-byte basis
by specifying the low or high byte in an instruction which
accesses the SFRs. See application note AN458 for more
details.
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