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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 74/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
74
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
The CPU interfaces to the I
2
C logic via the following four
special function registers: S1CON (SIO1 control register),
S1STA (SIO1 status register), S1DAT (SIO1 data
register), and S1ADR (SIO1 slave address register). The
SIO1 logic interfaces to the external I
2
C bus via two port 1
pins: P1.6/SCL (serial clock line) and P1.7/SDA (serial
data line).
A typical I
2
C bus configuration is shown in Figure 30, and
Figure 31 shows how a data transfer is accomplished on
the bus. Depending on the state of the direction bit (R/W),
two types of data transfers are possible on the I
2
C bus:
1.
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes.
The slave returns an acknowledge bit after each
received byte.
2.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an
acknowledge bit. Next follows the data bytes
transmitted by the slave to the master. The master
returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received
byte, a not acknowledge is returned.
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the
beginning of the next serial transfer, the I
2
C bus will not be
released.
15.1
The on-chip SIO1 logic may operate in the following four
modes:
1.
Master Transmitter Mode:
Serial data output through P1.7/SDA while P1.6/SCL
outputs the serial clock. The first byte transmitted
contains the slave address of the receiving device (7
bits) and the data direction bit. In this case the data
directionbit(R/W)willbelogic0,andwesaythata“W”
is transmitted. Thus the first byte transmitted is
SLA+W.Serialdataistransmitted8bitsatatime.After
each byte is transmitted, an acknowledge bit is
received. START and STOP conditions are output to
indicate the beginning and the end of a serial transfer.
Modes of Operation
2.
Master Receiver Mode:
Thefirstbytetransmittedcontainstheslaveaddressof
the transmitting device (7 bits) and the data direction
bit. In this case the data direction bit (R/W) will be logic
1, and we say that an “R” is transmitted. Thus the first
byte transmitted is SLA+R. Serial data is received via
P1.7/SDA while P1.6/SCL outputs the serial clock.
Serial data is received 8 bits at a time. After each byte
is received, an acknowledge bit is transmitted. START
and STOP conditions are output to indicate the
beginning and end of a serial transfer.
Slave Receiver Mode:
Serial data and the serial clock are received through
P1.7/SDA and P1.6/SCL. After each byte is received,
an acknowledge bit is transmitted. START and STOP
conditions are recognized as the beginning and end of
a serial transfer. Address recognition is performed by
hardware after reception of the slave address and
direction bit.
Slave Transmitter Mode:
The first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction bit
will indicate that the transfer direction is reversed.
Serial data is transmitted via P1.7/SDA while the serial
clock is input through P1.6/SCL. START and STOP
conditions are recognized as the beginning and end of
a serial transfer.
In a given application, SIO1 may operate as a master and
as a slave. In the slave mode, the SIO1 hardware looks for
its own slave address and the general call address. If one
of these addresses is detected, an interrupt is requested.
When the microcontroller wishes to become the bus
master, the hardware waits until the bus is free before the
master mode is entered so that a possible slave action is
notinterrupted.Ifbusarbitrationislostinthemastermode,
SIO1 switches to the slave mode immediately and can
detect its own slave address in the same serial transfer.
3.
4.
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