參數(shù)資料
型號： P8XC591
廠商： NXP Semiconductors N.V.
英文描述： HiRel FPGA, Low-Power 1.0?? CMOS Technology
中文描述： 單芯片8 - CAN控制器位微控制器
文件頁數(shù)： 125/160頁
文件大?。?/td> 601K
代理商： P8XC591
2000 Jul 26
125
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
Fig.48 Functional diagram of Analog Input Circuitry.
handbook, full pagewidth
MHI050
INTERNAL BUS
ANALOG INPUT
MULTIPLEXER
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
n.c.
n.c.
ANALOG GROUND
ANALOG REF.
+
1
2
0
4
5
6
7
3
10-BIT A/D CONVERTER
1
2
0
4
5
6
7
ADCH
ADCON
3
20.3
10-Bit Analog-to-Digital Conversion
Figure 48 shows the elements of a successive
approximation (SA) ADC. The ADC contains a DAC which
converts of a successive approximation register to a
voltage (VDAC) which is compared to the analog input
voltage (V
IN
). The output of the comparator is fed to the
successive approximation control logic which controls the
successive approximation register. A conversion is
initiated by setting ADCS in ADCON register. ADCS can
bet set by software only.
The software start mode is selected when control bit
ADCON.5 (ADEX) = 0. A conversion is then started by
setting control bit ADCON.3 (ADCS). The software start
mode is selected when ADCON.5 = 1, and a conversion
may be started by setting ADCON.3.
When a conversion is initiated, the conversion starts at the
beginning of the machine cycle which follows the
instruction that sets ADCS. ADCS is actually implemented
with two flip-flops; a command flip-flop which is affected by
set operations, and a status flag which is accessed during
read operations.
The next two machine cycles are used to initiate the
converter. At the end of the first cycle, the ADCS status
flag is set and a value of “1” will be returned if the ADCS
flag is read while the conversion is progress. Sampling of
the analog input commences at the end of the second
cycle.
During the next eight machine cycles, the voltage at the
previously selected pin of port 1 is sampled, and this input
voltageshouldbestableinordertoobtainausefulsample.
In any event, the input voltage slew rate must be less than
10 V/ms in order to prevent an undefined result.
The successive approximation control logic first sets the
most significant bit and clears all other bits in the
successive approximation register (10 0000 0000B). The
output of the DAC (50% full scale) is compared to the input
voltage V
IN
. If the input voltage is greater than VDAC, then
the bit remains set; otherwise it is cleared.
The successive approximation control logic now sets the
next most significant bit (11 0000 0000B or
01 0000 0000B, depending on the previous result), and
VDAC is compared to V
IN
again. If the input voltage is
greater than VDAC, then the bit being tested remains set;
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