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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 86/160頁(yè) |
| 文件大?。?/td> | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
86
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
master of the bus. In other words, if AA is reset, SIO0
cannot enter a slave mode. STA, STO, and SI must be
reset.
The master transmitter mode may now be entered by
setting the STA bit using the SETB instruction. The SIO1
logic will now test the I
2
C bus and generate a start
condition as soon as the bus becomes free. When a
START condition is transmitted, the serial interrupt flag
(SI) is set, and the status code in the status register
(S1STA) will be 08H. This status code must be used to
vectortoaninterruptserviceroutinethatloadsS1DATwith
the slave address and the data direction bit (SLA+W). The
SI bit in S1CON must then be reset before the serial
transfer can continue.
When the slave address and the direction bit have been
transmitted and an acknowledgment bit has been
received, the serial interrupt flag (SI) is set again, and a
number of status codes in S1STA are possible. There are
18H, 20H, or 38H for the master mode and also 68H, 78H,
or B0H if the slave mode was enabled (AA = logic 1). The
appropriate action to be taken for each of these status
codes is detailed in Table 61. After a repeated start
condition (state 10H). SIO1 may switch to the master
receiver mode by loading S1DAT with SLA+R).
Table 58
Address Register S1CON (address D8H)
7
6
5
4
3
2
1
0
CR2
bit rate
ENS1
1
STA
0
STO
0
SI
0
AA
X
CR1
CR0
bit rate
15.2.14.2 Master Receiver Mode
In the master receiver mode, a number of data bytes are
received from a slave transmitter (see Figure 38). The
transfer is initialized as in the master transmitter mode.
When the start condition has been transmitted, the
interrupt service routine must load S1DAT with the 7-bit
slave address and the data direction bit (SLA+R). The SI
bit in S1CON must then be cleared before the serial
transfer can continue.
When the slave address and the data direction bit have
been transmitted and an acknowledgment bit has been
received, the serial interrupt flag (SI) is set again, and a
number of status codes in S1STA are possible. These are
40H, 48H, or 38H for the master mode and also 68H, 78H,
or B0H if the slave mode was enabled (AA = logic 1). The
appropriate action to be taken for each of these status
codes is detailed in Table 62. ENS1, CR1, and CR0 are
not affected by the serial transfer and are not referred to in
Table 62. After a repeated start condition (state 10H),
SIO1 may switch to the master transmitter mode by
loading S1DAT with SLA+W.
15.2.14.3 Slave Receiver Mode:
In the slave receiver mode, a number of data bytes are
received from a master transmitter (see Figure 39). To
initiate the slave receiver mode, S1ADR and S1CON must
be loaded as in Table 59.
The upper 7 bits are the address to which SIO1 will
respond when addressed by a master. If the LSB (GC) is
set, SIO1 will respond to the general call address (00H);
otherwise it ignores the general call address.
CR0, CR1, and CR2 do not affect SIO1 in the slave mode.
ENS1 must be set to logic 1 to enable SIO1. The AA bit
must be set to enable SIO1 to acknowledge its own slave
address or the general call address. STA, STO, and SI
must be reset.
When S1ADR and S1CON have been initialized, SIO1
waits until it is addressed by its own slave address
followed by the data direction bit which must be “0” (W) for
SIO1 to operate in the slave receiver mode. After its own
slave address and the W bit have been received, the serial
interrupt flag (I) is set and a valid status code can be read
from S1STA. This status code is used to vector to an
interrupt service routine, and the appropriate action to be
taken for each of these status codes is detailed in
Table 63. The slave receiver mode may also be entered if
arbitration is lost while SIO1 is in the master mode (see
status 68H and 78H).
If the AA bit is reset during a transfer, SIO1 will return a not
acknowledge (logic 1) to SDA after the next received data
byte. While AA is reset, SIO1 does not respond to its own
slave address or a general call address. However, the I
2
C
bus is still monitored and address recognition may be
resumedatanytimebysettingAA.ThismeansthattheAA
bit may be used to temporarily isolate SIO1 from the I
2
C
bus.
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