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PRELIMINARY
XRT79L71
210
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: The LOS Clearance criteria for Receive DS3/E3 LIU Block will be discussed in Section 4.3.1.6. Configuration Options for the LOS Declaration/Clearance Criteria
The Receive DS3/E3 Framer block within the XRT79L71 permits the user to change the LOS Declaration
criteria such that the LOS defect condition is declared only if the Receive DS3/E3 LIU Interface declares the
LOS defect condition. If this configuration selection is implemented, then the internally-generated LOS criteria
of 180 consecutive "0s" will be disabled. The user can accomplish this configuration selection by writing a "0"
to bit 3 (Internal LOS Enable) within the Operating Mode Register, as depicted below.
4.3.2.3.3
The Relationship between the LOS Defect condition being declared or cleared in the Receive
DS3/E3 LIU Block and in the Receive DS3/E3 Framer Block
4.3.2.4
DECLARING AND CLEARING THE AIS DEFECT CONDITION
The Receive DS3/E3 Framer block has the responsibility for declaring and clearing the AIS (Alarm Indication
Signal) defect, as described below.
The AIS Patterns that are supported by the Receive DS3/E3 Framer block
The Receive DS3 Framer block can be configured to declare the AIS defect condition, in response to detecting
either of the following types of AIS patterns.
The Bellcore GR-499-CORE standard AIS signal.
The Relaxed Bellcore GR-499-CORE standard AIS signal
The Unframed, All Ones AIS signal
The steps to configuring the Receive DS3/E3 Framer block into each of these modes will be presented below.
Declaring the AIS Defect condition, in response to only the Bellcore GR-499-CORE standard AIS signal
The Receive DS3 Framer block can be configured such that it will identify and declare the AIS defect condition
if it detects all of the following conditions in the incoming DS3 data-stream:
Valid M-bits, F-bits and P-bits
All C-bits are zeros.
X-bits are set to "1"
Receive DS3 Interrupt Status Register (Address = 0x1113)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
CP Bit Error
Interrupt
Status
Change of
LOS Defect
Condition
Interrupt
Status
Change of
AIS Defect
Condition
Interrupt
Status
Change of
Idle Condi-
tion Inter-
rupt
Status
Change of
FERF Defect
Condition
Interrupt
Status
Change of
AIC State
Interrupt
Status
Change of
OOF Defect
Condition
Interrupt
Status
Detection of
P-Bit Error
Interrupt
Status
RUR
0
1
0
Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local Loop
Back
IsDS3
Internal LOS
Enable
RESET
Direct
Mapped ATM
Frame For-
mat
TimRefSel[1:0]
R/W
0
1
0
1