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PRELIMINARY
XRT79L71
34
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
5.
Next, the mC/uP should then place the byte that it intends to write into the "target" register (or buffer/
memory location) into the XRT79L71, on the bi-directional data bus pins (D[7:0]).
6.
Afterwards, the C/P should then indicate that this current bus cycle is a "Write" Operation; by toggling
the WR/R/W (Write Strobe) input pin "low". This action also enables the "bi-directional" data bus input
drivers of the XRT79L71. At this point, the "bi-directional" data bus input drivers will proceed to drive the
contents (currently residing on the Bi-Directional Data bus into the register (or buffer/memory location)
that corresponds with the "latched address".
7.
Immediately after the C/P toggles the "Write Strobe" (WR/R/W) signal "low", the XRT79L71 will
continue to drive the RDY/DTACK output pin "high". The XRT79L71 does this in order to inform the C/
P that the data (to be written into the "target" address location (within the XRT79L71) is "NOT READY"
to be latched into the C/P. In this case, the C/P should continue to hold the "Write Strobe" (WR/R/W)
input pin "low" until it detects the RDY/DTACK output pin toggling high.
8.
After waiting the appropriate amount of time, for the data (on the bi-directional data bus) to stabilize and
can be safely accepted by the C/P. At this time, the XRT79L71 will indicate that this data can be
latched into the "target" address location, by toggling the RDY/DTACK output pin "low".
9.
After the C/P detects the RDY/DTACK signal (from the XRT79L71) toggling "low", it can then terminate
the Write Cycle by toggling the WR/R/W (Write Strobe) input pin "high".
NOTE: Once the user toggles the "
WR/R/W (Write Strobe) input pin "high", then the Microprocessor Interface (of the
XRT79L71) will latch the contents of the bi-directional data bus (D[7:0]) into the "target" address location within the
chip.
Figure 7 presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during
an "Intel-Asynchronous" Mode Write Operation.
FIGURE 7. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING AN "INTEL-ASYNCHRONOUS" WRITE
OPERATION.
ALE/AS
A[14:0]
CS*
D[7:0]
WR*/R/W*
Data to be Written
Address of Target Register
RD*/DS*
RDY*/DTACK*
Microprocessor places “target”
Address value on A[14:0]
Microprocessor Interface latches contents on
A[14:0] upon falling edge of ALE
Address Decoding
Circuitry asserts
CS*
Write Operation begins
Here
RDY* toggles “l(fā)ow” to indicates
That valid data can be latched into
“target” Address location of chip
Write Operation is
Terminated Here
RDY* toggles “high” after
Completion of Write
Operation