![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_377.png)
PRELIMINARY
XRT79L71
362
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
The purpose of the SFM Synthesizer block is to provide the Clock and Data Recovery with a proper
"Reference" clock signal that is of the frequency 44.736MHz (for DS3 applications) or 34.368MHz (for E3
applications). The Clock and Data Recovery block will use this "Reference Clock" signal in order to determine
whether or not it should declare the "LOL" (Loss of Lock) Defect Condition.
The SFM Synthesizer block can be configured to operate in one of the following two modes.
The SFM (Single Frequency) Mode, or
The Multiplexer Mode
5.3.1.5.1
Operating the "SFM Synthesizer" Block in the "SFM" (Single-Frequency) Mode
If the "SFM Synthesizer" block is configured to operate in the "SFM" Mode, then the user is expected to
provide a 12.288MHz clock signal to the "DS3CLK/SFMCLK" input pin (Ball P16). The "SFM Synthesizer"
block will then accept this 12.288MHz clock signal, and it will synthesize either a 44.736MHz clock signal (if the
XRT79L71 has been configured to operate in the DS3 Mode), or it will synthesize a 34.368MHz clock signal (if
the XRT79L71 has been configured to operate in the E3 Mode). The Clock and Data Recovery will, in turn,
use this "synthesized" clock signal as its frequency reference, in order to determine whether or not it should
declare the LOL defect condition.
This mode is referred to as the "Single-Frequency" Mode, because the user only needs to supply a single clock
frequency (12.288MHz, in this case) to the DS3CLK/SFMCLK input pin, in order to permit the "SFM
Synthesizer" block to fully support all operational requirements of the XRT79L71. Figure 167 presents a
simple illustration that depicts how the "SFM Synthesizer" Block functions whenever it has been configured to
operate in the "SFM" Mode.
Configuring the SFM Synthesizer Block to operate in the SFM (Single-Frequency) Mode
The user can configure the "SFM Synthesizer" Block to operate in the SFM (Single-Frequency) Mode by
executing the following steps.
STEP 1 - Apply a 12.288MHz clock signal to the DS3CLK/SFMCLK Input pin (Ball P16)
STEP 2 - Tie the E3CLK input pin (Ball M16) to GND.
STEP 3 - Set Bit 5 (SFM Enable) within the "LIU Channel Control" Register, to "1" as depicted below.
FIGURE 167. A SIMPLE ILLUSTRATION THAT DEPICTS HOW THE "SFM SYNTHESIZER" BLOCK FUNCTIONS WHENEVER
IT HAS BEEN CONFIGURED TO OPERATE IN THE
"SFM" MODE
SFM
Synthesizer
Block
SFM
Synthesizer
Block
12.288MHz
44.736MHz
Or
34.368MHz
To Clock Recovery
PLL Block
DS3CLK/SFMCLK
(Ball P16)