![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_515.png)
PRELIMINARY
XRT79L71
500
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
STEP 2 - Configure the Transmit DS3/E3 Framer block to use the Transmit E3 MA Byte Register as the
source of content for the MA byte, within each outbound E3 frame.
This is accomplished by setting Bit 0 (Transmit MA Byte based upon Receive Conditions), within the Transmit
E3 Configuration Register to "0" as depicted below.
Once the user executes these two steps, then the Transmit DS3/E3 Framer block will begin to read out the
contents of the Transmit E3 MA Byte Register, and will be writing this particular value into the MA Byte, within
each outbound E3 frame. Bit 7, within the Transmit E3 MA Byte Register, corresponds to Bit 1 (FERF/RDI)
within the MA byte. Therefore, by setting Bit 7 within the Transmit E3 MA Byte Register to "1" the Transmit
DS3/E3 Framer block will set the FERF/RDI bit-field within the MA byte-field of each outbound E3 frame to "1".
This will result in the transmission of the FERF/RDI indicator to the remote terminal equipment.
6.2.6.3.2
Automatic Transmission of the FERF/RDI Indicator
The XRT79L71 permits the user to configure the Transmit E3 Framer block to automatically transmit the FERF/
RDI indicator, in response to any of the following conditions.
Whenever the corresponding near-end Receive DS3/E3 Framer block is declaring the LOS (Loss of Signal)
defect condition
Whenever the corresponding near-end Receive DS3/E3 Framer block is declaring the OOF (Out-of-Frame)
defect condition
Whenever the corresponding near-end Receive DS3/E3 Framer block is declaring the AIS defect condition.
The user can configure the Transmit DS3/E3 Framer block to automatically transmit the FERF/RDI indicator to
the remote terminal equipment, by setting Bit 0 (Transmit MA Byte based upon Receive Conditions) to "1" as
depicted below.
Transmit E3 MA Byte Register - G.832 (Direct Address = 0x1136)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxMA Byte[7:0]
R/W
1
0
Transmit E3 Configuration Register - G.832 (Direct Address = 0x1130)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TxDL in NR
Reserved
TxAIS
Enable
TxLOS
Enable
Transmit MA
Byte based
upon
Receive
Conditions
R/O
R/W
R/O
R/W
0