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XRT79L71
PRELIMINARY
77
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
The System-Side Terminal Equipment will serially output the payload data, that is to be transported via the
outbound DS3 data-stream, via its DS3_Data_Out output pin. The user is advised to design the System-Side
Terminal Equipment circuitry such that it will update the data via the DS3_Data_Out output pin upon the rising
edge of the 44.736MHz clock signal at its DS3_Clock_In input pin, as depicted below in Figure 33.
The XRT79L71 will latch the contents of the TxSer input pin, upon the rising edge of the TxInClk signal. In this
particular mode, the System-Side Terminal Equipment also has the responsibility of providing a Framing
Reference signal to the XRT79L71 by pulsing its TxFrameRef input pin "High" for one bit-period, coincident
with the first bit of a new outbound DS3 frame being applied to the TxSer input pin. Once the XRT79L71
detects the rising edge of the input at its TxFrameRef input pin, it will begin to generate and transmit a new
DS3 frame.
NOTES:
1.
In this particular mode, the System-Side Terminal Equipment is controlling the start of Frame Generation and is
referred to as the Frame Master. Since the XRT79L71 does not control or dictate the instant that it will generate a
new DS3 frame, but is driven by the System-Side Terminal Equipment, it is referred to as the Frame Slave.
2.
If the XRT79L71 is configured to operate in Mode 2 then it is imperative that the Tx_Start_of_Frame or
TxFrameRef signal is synchronized to the TxInClk input clock signal.
If the user fails to insure that the
TxFrameRef input signal is synchronized to the "TxInClk" input clock signal, then the XRT79L71 will transmit erred
DS3 data to the remote terminal equipment.
Finally, the XRT79L71 pulses its TxOH_Ind output pin "High" one bit-period prior to it processing a given
overhead bit within the outbound DS3 frame. Since the TxOH_Ind output pin of the XRT79L71 is electrically
connected to the DS3_Overhead_Ind input pin of the System-Side Terminal Equipment whenever the
XRT79L71 pulses its TxOH_Ind output pin "High", it will also drive the DS3_Overhead_Ind input pin of the
System-Side Terminal Equipment "High". Whenever the System-Side Terminal Equipment detects this pin
toggling "High" it should delay transmission of the very next DS3 payload bit by one TxInClk clock period.
Figure 33 presents an illustration of the System-Side Terminal Equipment/Transmit Payload Data Input
Interface signals for Mode 2 Operation.