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XRT79L71
PRELIMINARY
35
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
2.2
Operating the Microprocessor Interface in the Motorola-Asynchronous Mode
If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then the
following Microprocessor Interface pins will assume the role that is described below in Table 1c.
Configuring the Microprocessor Interface to operate in the Motorola-Asynchronous Mode
TABLE 5: THE ROLES OF VARIOUS MICROPROCESSOR INTERFACE PINS, WHEN CONFIGURED TO OPERATE IN THE
MOTOROLA-ASYNCHRONOUS MODE
PIN NAME
PIN/BALL
NUMBER
TYPE
DESCRIPTION
ALE/AS
A16
I
Address Strobe Input - AS
If the Microprocessor Interface has been configured to operate in the
Motorola-Asynchronous Mode, then this active-low input pin is used to
latch the data (residing on the Address Bus, A[14:0]) into the Microproces-
sor Interface circuitry of the XRT79L71.
Pulling this input pin "low" enables the input bus drivers for the Address
Bus input pins. The contents of the Address Bus will be latched into the
Microprocessor Interface circuitry, upon the rising edge of this input sig-
nal.
RD/DS/WE
C15
I
Data Strobe Input - RD
If the Microprocessor Interface is operating in the Motorola-Asynchronous
Mode, then this input pin will function as the DS (Data Strobe) input signal.
RDY/DTACK/RDY
C14
O
Data Transfer Acknowledge Output - DTACK
If the Microprocessor Interface has been configured to operate in the
Motorola-Asynchronous Mode, then this output pin will function as the
"active-low" DTACK output.
During a READ or WRITE cycle, the Microprocessor Interface block will
toggle this output pin to the logic low level, ONLY when it (the Micropro-
cessor Interface) is ready to complete or terminate the current READ or
WRITE cycle. Once the Microprocessor has determined that this input pin
has toggled to the logic "low" level, then it is now safe for it to move on
and execute the next READ or WRITE cycle.
If (during a READ or WRITE cycle) the Microprocessor Interface block is
holding this output pin at a logic "high" level, then the Microprocessor is
expected to extend this READ or WRITE cycle, until it detects this output
pin being toggled to the logic low level.
PCLK
H16
I
NONE - Tie to GND
WR/R/W
B16
I
Read/Write Operation Identification Input - R/W
If the Microprocessor Interface is operating in the "Motorola-Asynchro-
nous Mode", then this pin is functionally equivalent to the "R/W" input pin.
In the Motorola Mode, a "READ" operation occurs if this pin is held at a
logic "1", coincident to a falling edge of the
RD/DS (Data Strobe) input
pin. Similarly a WRITE operation occurs if this pin is at a logic "0", coinci-
dent to a falling edge of the
RD/DS (Data Strobe) input pin.
DBEN
J13
I
Data Bus Enable Input:
For Intel-Asynchronous Mode operation, either tie this pin to a logic "low"
or assert this pin (e.g., toggle it to a logic "low") anytime a READ opera-
tion is being performed with the Microprocessor Interface of the
XRT79L71.
BLAST
B15
I
NONE - Tie this pin to GND