![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_186.png)
XRT79L71
PRELIMINARY
171
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Conversely, to disable the Transmit Line Driver block, then the user should set Bit 0 (TxON) within the LIU
Transmit APS/Redundancy Control Register to "0" as depicted below.
NOTES:
1.
If this configuration setting is implemented, then the TTIP and TRING output pins of the XRT79L71 will be tri-
stated.
2.
To control the ON/OFF state of the Transmit Line Driver within the XRT79L71, via software command then the
user MUST make sure that the TxON input pin (Ball R15) is pulled to a logic "High".
3.
To implement the XRT79L71 into a DS3 Redundancy design, then executing a write to this particular register,
either enabling or disabling the Transmit Output will be required.
4.2.6.6
The Transmit Drive Monitor Block
The Transmit Drive Monitor block permits the user to monitor the Transmit Output signal, for continuous bipolar
signal activity, and can be used to (perhaps) detect a fault condition, in the Transmit Output line.
Use of the Transmit Drive Monitor block is optional. However, to use this feature, there are two ways that the
user can implement this feature.
Externally, and
Internally
4.2.6.6.1
Implementing the Transmit Drive Monitor via External Means
To implement Transmit Drive Monitoring via External Means, then this means that the Transmit Drive Monitor
block will be monitoring (e.g., checking for bipolar activity) within the Transmit Output line signal via the MTIP
and MRING input pins. To implement Transmit Drive Monitoring via External Means, the user must execute
the following steps.
STEP 1 - Design the Hardware such that (1) the MTIP ball is connected to the TTIP signal through a
274
resistor, connected in series, and (2) that the MRING ball is electrically connected to the TRING
signal through a 274
resistor, connected in series.
These connections are also depicted in the Schematic design below in Figure 78,
LIU Transmit APS/Redundancy Control Register (Address = 0x1300)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TxON
R/O
R/W
0