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XRT79L71
PRELIMINARY
541
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Terminal will set Bits 6 and 7 to the appropriate value, in order to "identify" this SSM bit, as depicted below in
6.3.4.2
CONFIGURING THE XRT79L71 TO RECEIVE SYNCHRONIZATION STATUS MESSAGES
To enable the Receive SSM Controller block (within the XRT79L71) and configure it to repeatedly receive the
SSM from the remote terminal equipment, execute the following two steps.
STEP 1 - Make sure that the XRT79L71 has been configured to operate in the E3, ITU-T G.832 Framing
Format.
This can be accomplish this by setting Bit 6 (IsDS3) to "0" and by setting Bit 2 (Frame Format) to "1" as
depicted below.
STEP 2 - Enable the Receive SSM Controller Block
This is accomplished by setting Bit 7 (RxSSM Enable) to "1" as depicted below.
Once these two steps have been executed, then the Receive SSM Controller block will be enabled, and will
now be capable of receiving SSM Messages from the remote terminal equipment.
6.3.4.3
READING OUT THE SSM FROM THE XRT79L71
The user can read out the contents of the most recently received SSM (by the Receive SSM Controller block)
by reading out the contents of Bits 3 through 0 (RxSSM[3:0]), within the "Receive E3 SSM Register - G.832" as
depicted below.
TABLE 67: THE RELATIONSHIP BETWEEN THE STATES OF BITS 6 AND 7 (WITHIN THE MA BYTE) AND THE EXACT
SSM BIT THAT IS BEING TRANSPORTED VIA BIT 8, WITHIN THE CURRENT MA BYTE
MA BYTE,
BIT 6
MA BYTE, BIT 7
THE SSM BIT BEING TRANSPORTED IN BIT 8
0
0
SSM Bit 1 (The MSB)
0
1
SSM Bit 2
1
0
SSM Bit 3
1
1
SSM Bit 4 (The LSB)
Framer Operating Mode Register (Address = 0x1100)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Local
Loop Back
IsDS3
Internal
LOS
Enable
RESET
Direct
Mapped
ATM
Frame
Format
TimRefSel[1:0]
R/W
0
1
0
1
Receive E3 SSM Register - G.832 (Address = 0x112C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxSSM
Enable
MF[1:0]
Reserved
RxSSM[3:0]
R/W
R/O
1
0