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XRT79L71
PRELIMINARY
537
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
NOTES:
1.
The contents within the "Receive Trail-Trace Message Register - Byte 1" will typically be of the [1, C6, C5, C4, C3,
C2, C1, C0]. The "1" within the MSB (most significant bit) position of this byte is used to designate that this octet
is the "Frame-Start Marker" byte (e.g., the very first of 16 TR byte, within a "Trail-Trace Message" Super-Frame)
within the "incoming" Trail-Trace Message. The remaining seven bits (e.g., C6 through C0) is typically the result of
a CRC-7 calculation that was computed over the previous "Trail-Trace Message" Super-Frame) from the remote
terminal equipment.
2.
The circuitry within the XRT79L71 will NOT compute and verify this CRC-7 value. To support this feature, then do
so externally.
Receive E3 Trail-Trace Message Byte 1 Register - G.832 (Address = 0x111C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB_Byte_1
R/W
1
C6
C5
C4
C3
C2
C1
C0
Receive E3 Trail-Trace Message Byte 2 Register - G.832 (Address = 0x111D)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB_Byte_2
R/W
0
A6
A5
A4
A3
A2
A1
A0
Receive E3 Trail-Trace Message Byte 3 Register - G.832 (Address = 0x111E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB_Byte_3
R/W
0
B6
B5
B4
B3
B2
B1
B0
Receive E3 Trail-Trace Message Byte 4 Register - G.832 (Address = 0x111F)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB_Byte_4
R/W
0
C6
C5
C4
C3
C2
C1
C0
Receive E3 Trail-Trace Message Byte 5 Register - G.832 (Address = 0x1120)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RxTTB_Byte_5
R/W
0
D6
D5
D4
D3
D2
D1
D0