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| 型號(hào)： | XRT79L71IB-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 86/609頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU/FRAMER DS3/E3 1CH 208BGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 控制器類(lèi)型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 208-LBGA |
| 供應(yīng)商設(shè)備封裝： | 208-STBGA（17x17） |
| 包裝： | 托盤(pán) |
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XRT79L71
PRELIMINARY
161
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
power-up or reset, the FIFO_WRITE pointer will have revolved around the circular buffer and will incremented
its location back to its initial (e.g., 12 o'clock) position.
Figure 73 also indicates that the initial position of the FIFO_READ pointer is at the 6 o'clock position. Further,
Figure 73 indicates that during the very next Out_CLK period the FIFO_READ pointer will have moved (in a
clockwise direction) to the position labeled FIFO_READ pointer at Out_CLK period k + 1.
If the FIFO Depth is configured to be 16 bits, then in 16 Out_CLK cycles, after power-up or reset, the
FIFO_READ pointer will have revolved around the circular buffer and have incremented its position right back
to the 6 o'clock position) as is shown in Figure 73. Similarly, if the FIFO depth is configured to be 32 bits, then
in 32 Out_CLK cycles, after power-up or reset, the FIFO_READ pointer will have revolved around the circular
buffer and will have incremented its location back to its initial (e.g., 6 o'clock) position.
Recall that the Out_CLK (smoothed) output clock signal is derived from a PLL that has a very narrow
bandwidth.
Therefore, the Jitter Attenuator PLL will not be very responsive to instantaneous phase or
frequency deviations that occur within the In_CLK (jittery) input clock signal. As the Jitter Attenuator PLL
experiences large phase variations (via the In_CLK input pin) it will typically not pass along these large phase
changes and variations to the Out_CLK output signal. This phenomenon will result in some modulation in the
distance between the FIFO_WRITE and FIFO_READ pointers. If the modulation in the distance (between the
FIFO_WRITE and FIFO_READ pointers) is such that the distance between these two pointers approach 0 bits,
then bit-errors will occur. This modulation in the distance between the FIFO_WRITE and FIFO_READ pointers
and its effect on the integrity of the data is described in some detail below.
The FIFO Under-run Condition
If the jitter within the In_CLK input clock signal is such that, for a very short period of time, the instantaneous
frequency of In_CLK deviates, in the negative direction, (e.g., exhibits a lower frequency from that of the
Out_CLK output clock signal) then the following events will happen.
The Jitter Attenuator PLL will continue to generate the Out_CLK output clock signal at virtually a constant
rate (e.g., with very little change in frequency). As a consequence, the FIFO_READ pointer will continue to
increment and revolve about the circular buffer at largely a fixed rate.
Because the In_CLK input clock signal is, for a very short period, of a lower frequency, the FIFO_WRITE
pointer will now be incremented, around the circular buffer, at a lower rate than that of the FIFO_READ
pointer.
If the above-mentioned condition were to exist long enough, the FIFO_READ pointer will eventually revolve
around the circular buffer, and catch-up with the FIFO_WRITE pointer. If this happens, then a FIFO Under-run
condition will be said to have occurred. In a FIFO Under-run Condition, all new data that has been written into
the Jitter Attenuator FIFO has been read out and depleted. At this point, the Jitter Attenuator block is now
reading out data which has already been read out, at least once. This phenomenon will cause the XRT79L71
to transmit erroneous data to the remote terminal equipment.
The FIFO Overflow Condition
If the jitter within the In_CLK input clock signal is such that, for a very short period of time, the instantaneous
frequency of In_CLK deviates, in the positive direction, (e.g., exhibits a much higher frequency from that of the
Out_CLK output clock signal) then the following events will happen.
The Jitter Attenuator PLL will continue to generate the Out_CLK at virtually a constant rate (e.g., with very
little change in frequency). As a consequence, the FIFO_READ pointer will continue to increment and
revolve about the circular buffer at largely a fixed rate.
Because the In_CLK input clock signal is, for a very short period, of a higher frequency, the FIFO_WRITE
pointer will now be incremented, around the circular buffer, at a higher rate than that of the FIFO_READ
pointer.
If the above-mentioned condition were to exist long enough, the FIFO_WRITE pointer will eventually revolve
around the circular buffer, and catch-up with the FIFO_READ pointer. If this happens, then an Overflow
condition will be said to have occurred. In an Overflow condition, new data has been written into locations
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