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XRT79L71
PRELIMINARY
109
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
TABLE 21: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE TXOHENABLE SIGNAL, SINCE THE
TXOHFRAME SIGNAL WAS LAST SAMPLED "HIGH" TO THE DS3 OVERHEAD BIT THAT IS CURRENTLY BEING
PROCESSED BY THE
TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK
NUMBER OF PULSES IN TXOHENABLE,
SINCE
TXOHFRAME BEING SAMPLED
"HIGH"
THE OVERHEAD BIT TO BE PROCESSED
BY THE
TRANSMIT OVERHEAD DATA
INPUT INTERFACE BLOCK
CAN THIS OVERHEAD BIT BE ACCEPTED BY
THE
XRT79L71, AND INSERTED INTO THE
OUTBOUND
DS3 DATA-STREAM?
0 (TxOHEnable and TxOHFrame are
sampled "High" simultaneously)
X Bit # 1
YES
1
F1
NO
2
AIC (C11)
YES
3
F0
NO
4
NA (C12)
YES
5
F0
NO
6
FEAC (C13)
YES
7
F1
NO
8
X Bit # 2
YES
9
F1
NO
10
UDL Bit # 1 (C21)
YES
11
F0
NO
12
UDL Bit # 2 (C22)
YES
13
F0
NO
14
UDL Bit # 3 (C23)
YES
15
F1
NO
16
P
NO
17
F1
NO
18
CP Bit # 1 (C31)
YES
19
F0
NO
20
CP Bit # 2 (C32)
YES
21
F0
NO
22
CP Bit # 3 (C33)
YES
23
F1
NO
24
P
NO
25
F1
NO
26
FEBE # 1 (C41)
YES
27
F0
NO
28
FEBE # 2 (C42)
YES