XENPAK LASI AND DOM REGISTERS (1.9000’H TO 1.9007’H & 1.A000’H TO 1.A100’H) Note (1): Where two values are given, Default depends on LX4/CX" />
參數(shù)資料
型號： BBT3821-JH
廠商： Intersil
文件頁數(shù)： 20/75頁
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
27
XENPAK LASI AND DOM REGISTERS (1.9000’H TO 1.9007’H & 1.A000’H TO 1.A100’H)
Note (1): Where two values are given, Default depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value. The value may be overwritten by the Auto-
Note (1): Where two values are given, Default depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value. The value may be overwritten by the Auto-
Note (1): The default values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). Since
on Power up or RESET several LASI contributors will initially be in the ‘fault’ condition (in particular, Byte Synch and Lane Alignment, and their derivatives), it
may be advisable for a host to clear these before enabling these to trigger LASI.
Note (2): See description of the General Purpose Input/Output (GPIO) pins and bits for a description of how they contribute to the LASI system.
Table 24. XENPAK LASI RX_ALARM CONTROL REGISTER
MDIO REGISTER, ADDRESS = 1.36864 (1.9000’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.36864.15:7
Reserved
000’h
1.36864.6
PCS Byte S
1 = trigger LASI by
corresponding bit of
1.36867 (1.9003’h)
0 = LASI ignores
corresponding bit of
1.36867 (1.9003’h)
0’b
R/W
PCS Byte Sync Fail LASI Enable
1.36864.5
RX Power
1’b
R/W
Receive Laser Pwr/Sig Det LASI Enable
1.36864.4
PMA LF
1’b
R/W
PMA RX Local Fault LASI Enable
1.36864.3
PCS LF
1’b
R/W
PCS RX Local Fault LASI Enable
1.36864.2
PCS Code
0’b/1’b
R/W
8b/10b Code Violation LASI Enable
1.36864.1
DOM RX
1’b
R/W
DOM RX or RX EFIFO Fault LASI Enable
1.36864.0
PHY RX LF
1’b
R/W
PHY RX Local Fault LASI Enable
Table 25. XENPAK LASI TX_ALARM CONTROL REGISTER
MDIO REGISTER, ADDRESS = 1.36865 (1.9001’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.36865.15:11
Reserved
000’h
1.36865.10
PHY S_D
1 = trigger LASI from
corresponding bit of
1.36868 (1.9004’h)
0 = LASI ignores
corresponding bit of
1.36868 (1.9004’h)
0’b/1’b
R/W
PHY XS Signal Detect LASI Enable
1.36865.9
LBC
1’b/0’b
R/W
Laser Bias Current Fault LASI Enable
1.36865.8
LTEMP
1’b/0’b
R/W
Laser Temperature Fault LASI Enable
1.36865.7
LOP
1’b/0’b
R/W
Laser Output Power Fault LASI Enable
1.36865.6
TX LF
1’b/0’b
R/W
Transmit Local Fault LASI Enable
1.36865.5
Byte Sync
0’b/1’b
R/W
PHY XS Byte Sync Fail LASI Enable
1.36865.4
PMA LF
1’b
R/W
PMA TX Local Fault LASI Enable
1.36865.3
PCS LF
1’b/0’b
R/W
PCS TX Local Fault LASI Enable
1.36865.2
TX EFIFO
0’b/1’b
R/W
Transmit EFIFO Error LASI Enable
1.36865.1
DOM TX/
PHY Code
1’b
R/W
DOM TX or PHY XS 8b/10b Code Violation Fault LASI
Enable
1.36865.0
PHY TX LF
1’b
R/W
PHY TX Local Fault LASI Enable
Table 26. XENPAK LASI CONTROL REGISTER
MDIO REGISTER, ADDRESS = 1.36866 (1.9002’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.36866.15:4
Reserved
000’h
1.36866.3
GPIO
1 = trigger LASI via bit in
1.36869 (1.9005’h)
0 = LASI ignores bit
0’b
R/W
Enable GPIO pins to trigger LASI(2)
1.36866.2
RX_Alarm
0’b
R/W
Enable RX_Alarm to trigger LASI
1.36866.1
TX_Alarm
0’b
R/W
Enable TX_Alarm to trigger LASI
1.36866.0
LS_Alarm
0’b
R/W
Enable Link Status change to trigger LASI
BBT3821
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