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參數(shù)資料
| 型號(hào)： | BBT3821-JH |
| 廠(chǎng)商： | Intersil |
| 文件頁(yè)數(shù)： | 35/75頁(yè) |
| 文件大小： | 0K |
| 描述： | IC RE-TIMER OCTAL 192-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類(lèi)型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 無(wú) |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.1875Gbps |
| 電源電壓： | 1.425 V ~ 2.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應(yīng)商設(shè)備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤(pán) |
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40
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
Note (1): The status of these bits depends on the signal conditions. Default shown is for normal operation. The bits contribute to the RX Local Fault bit, see Table 60.
Note (2): See Note (1) to Table 57, Note (2) to Table 64 and/or “PCS (Parallel) Loopback (4.C004.[3:0] & Optionally 3.0.14)” under “Loopback Modes ” on page 13. If
enabled, this register bit does NOT conform to the IEEE 802.3ae-2002 specification.
Note (1): For other test pattern generation capabilities incorporated in the BBT3821, including CJPAT and CRPAT, see Table 72.
Table 60. IEEE PCS STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER
MDIO REGISTER ADDRESS = 3.8 (3.0008’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
3.8.15:14
Device present
10 = Device present
10’b
RO
When read as “10”, it indicates that a device is
present at this device address
3.8.13:12
Reserved
3.8.11
TX LocalFlt
1 = TX Local Fault; on Egress
channel
0’b
RO LH(1)
PLL Lock Failure is only PCS TX Fault
3.8.10
RX LocalFlt
1 = RX Local Fault; on Ingress
channel
0’b
RO LH(1)
Lane Alignment or Byte Alignment not done, or
Loss of Signal, from Register 3.24 (3.0018’h)
3.8.9:3
Reserved
3.8.2
10GBASE-W
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-W
3.8.1
10GBASE-X
1 = can perform
1’b
RO
Device can perform 10GBASE-X
3.8.0
10GBASE-R
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-R
Table 61. IEEE 10GBASE-X PCS STATUS REGISTER
MDIO REGISTER ADDRESSES = 3.24 (3.0018’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
3.24.15:13
Reserved
3.24.12
Lane_Align
1 = 4 Lanes Aligned
0 = Lanes not aligned
1’b(1)
RO
1 = All four 3G receive lanes (on ingress path) are
aligned
3.24.11
Test_Pattern
Test Pattern Abilities
1’b
RO
1 = The device is able to generate test patterns for
10GBASE-X
3.24.10
PCS Loopback
Ability(2) or
Reserved
1 = has Optional PCS
Loopback Ability.
0’b
RO
If enabled by EN_PCS_LB (see bit 3.C001’h.7,
Table 64) indicates PCS Loopback ability, and is a
1‘b bit; otherwise, a reserved 0’b bit (2).
3.24.9:4
Reserved
00’h
3.24.3
Lane3 Sync
1 = PCS Lane is Synchronized
0 = PCS Lane not
Synchronized
1’b(1)
RO
Reflects the PCS_SYNC byte alignment state
machine condition; not valid if not enabled in
device (see Table 63)
3.24.2
Lane2 Sync
1’b(1)
RO
3.24.1
Lane1 Sync
1’b(1)
RO
3.24.0
Lane0 Sync
1’b(1)
RO
Table 62. IEEE 10GBASE-X PCS TEST CONTROL REGISTER
MDIO REGISTER ADDRESS = 3.25 (3.0019’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
3.25.15:3
Reserved
3.25.2
PCS TestPatEn
Transmit Test Pattern
Enable
0’b
R/W
0 = Do not Transmit test pattern
1 = Transmit test pattern
3.25.1:0
PCS TestPat
Type
Test pattern
select
00’b
R/W
11 = Reserved
10 = Mixed frequency test pattern (Continuous /K/ = K28.5)
01 = Low frequency test pattern (repeat 0000011111 = K28.7)
00 = High frequency test pattern (repeat 0101010101 = D10.2)
BBT3821
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