many TOSA, ROSA and lane-oriented DOM devices have open-drain outputs that go high on an alarm condition, wire- AND-ing these together for a fo" />
參數(shù)資料
型號： BBT3821-JH
廠商： Intersil
文件頁數(shù)： 72/75頁
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標準包裝： 90
類型： 時鐘和數(shù)據(jù)恢復（CDR），多路復用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應商設備封裝： 192-EBGA-B（17x17）
包裝： 托盤
74
many TOSA, ROSA and lane-oriented DOM devices have
open-drain outputs that go high on an alarm condition, wire-
AND-ing these together for a four-lane indication is not
possible (any ‘working’ lane masks the ‘a(chǎn)larmed’ lane(s)),
some external gating may be required (typically a 4-input OR
or NOR gate per alarm). Note that the default polarity of
these alarm inputs (active high) will be set after power-up,
RESET or a hard (D.0.15) software reset, until the device is
reconfigured. If a host-driven configuration is being used, the
polarities (controlled by 1.C01D, Table 55) should be set
before the LASI enables (1.9002, Table 27). If the Auto-
Configure system is used (See “Auto-Configuring Control
Registers” on page 16 and Table 92), the configuration may
take typically about 100 msec (see Figure 18 and Table 117),
and there will normally be a brief interval during which the
LASI interrupt is likely to be (incorrectly) activated. LASI host
operations would probably normally ignore such ‘glitches’,
since the Byte Synch and Lane Alignment will initially be in
‘Fault’ condition after such a RESET (per the IEEE 802.3ae
specification), and so the relevant latched Local Fault
indications will need to be cleared before LASI is
meaningful, but it could be advisable to ensure that the
additional indications are ignored or cleared in the same way
before the full LASI system is activated.
R1
68
D1
ZHCS400
A
B
P3V3
VDDPR
U1
LMV431
2
1
3
Reference
VDD
R2
10K
From MSA Conn
To BBT3821,
Pull-Up Resistors
R3
12K
FIGURE 25. VDDPR CLAMP CIRCUIT
Cathode
Anode
Cathode
Anode
Rpu
12K
TX_FAULT_3P3
-- -each-- -
18K for
MIC3000
TX_FAULT
Rpu
12K
-- - etc. - - -
SDA, SCL
TX_ENA3P3_#
Rpu
12K
Rpu
12K
RAW_3V3
TX_FAULT_3P3
TX_ENA#
Rpu
12K
SDA, SCL
RAW_3V3
Rpd
10K
OPRXOP
OPRXOP_3P3
From
B
T3
821
Rpd
30K
Rpd
10k
Rpd
16K
OPRXOP
Rpd
10K
RAW_3V3
-- -etc.- - -
- --etc.-- -
TX_FAULT
Rpd
10k
OPRXOP_3P3
Rpu
12K
- - -etc.- --
T
o
/
F
ro
m
3.
3V
E
P
R
O
M
F
ro
m
/
T
o
B
T
38
2
1
T
o
3
.3
V
T
O
S
A
F
ro
m
3
.3
V
O
S
A
(O
p
e
n
D
ra
in
o
n
ly
)
F
ro
m
3
.3
V
O
S
A
(A
c
ti
v
e
P
u
ll
u
p
)
FIGURE 26. RESISTIVE DIVIDER CIRCUITS
BBT3821
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