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參數(shù)資料
| 型號： | BBT3821-JH |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/75頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RE-TIMER OCTAL 192-BGA |
| 標準包裝： | 90 |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 無 |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.1875Gbps |
| 電源電壓： | 1.425 V ~ 2.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應商設備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤 |
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14
PHY XS (Serial) Loopback (4.0.14 & 4.C004.[11:8])
The PHY XS loopback is implemented from the output of the
TXP[3:0] serializers to the input multiplexers in front of the
RXP[3:0] CDRs. All four lanes are controlled by bit 4.0.14,
while the individual lanes can be controlled (one at a time) by
the 4.C004’h.[11:8] bits. Assuming that this is the only
loopback enabled, and that the BIST and test pattern
generation features are not enabled, the signal flow is from
the RCX[3:0][P/N] pins through almost all the ‘ingress’
channel to the input of the (still active) TXP[3:0] output drivers,
then (bypassing the RXP[3:0][P/N] inputs, the equalizers and
LOS detectors) back from the CDRs through almost all the
‘egress’ channel to the TCX[3:0][P/N] pins.
PCS Parallel Network Loopback (3.C004.[3:0])
This loopback is implemented (at the internal XGMII-like level)
from the output of the RXFIFOs in the ‘ingress’ channel to the
input of the TXFIFOs in the ‘egress’ channel. The individual
lanes can be controlled (one at a time) by the 3.C004’h.[3:0]
bits. Assuming that this is the only loopback enabled, and that
the BIST and test pattern generation features are not enabled,
the signal flow is from the RCX[3:0][P/N] pins through the
PMA/PMD and PCS and again PMA/PMD to the
TCX[3:0][P/N] pins. This could also be seen as a ‘short’
loopback at the XGMII input of the PHY XS.
PCS (Parallel) Loopback (4.C004.[3:0] & Optionally
3.0.14)
This loopback is implemented (at the internal XGMII-like level)
from the output of the RXFIFOs in the ‘egress’ channel to the
input of the TXFIFOs in the ‘ingress’ channel. The individual
lanes can be controlled (one at a time) by the 4.C004’h.[3:0]
bits. If the enable bit in 3.C001.7 (Table 64) is set, all four
lanes can be controlled by bit 3.0.14. Since the latter is
specifically excluded by subclause 45.2.3.1.2 of the IEEE
802.3ae-2002 specification for a 10GBASE-X PCS, the
default is to NOT enable this loopback bit, and if it is enabled,
the BBT3821 does not conform to the IEEE specification. A
maintenance request has been submitted to the IEEE to
enable this loopback bit as optional, and to allow a ‘PCS
Loopback Capability’ bit in register bit 3.24.10 (see
http://www.ieee802.org/3/maint/requests/maint_1113.pdf), but
this has so far been rejected, and may never be approved.
Assuming that this is the only loopback enabled, and that the
BIST and test pattern generation features are not enabled, the
signal flow is from the RXP[3:0][P/N] pins through the full PHY
XS via the internal XGMII to the TXP[3:0][P/N] pins. This
could also be seen as a ‘short’ loopback at the XGMII input of
the PCS.
PLL LOCK
FAIL
IEEE REG
1.8.11
See LASI
TXFAULT
IEEE REG
1.1.7
IEEE REG
1.8.10
See LASI
IEEE REG
1.10.0
IEEE REG
1.10.4:1
CX4
LX4
OPRLOS
[3:0]
REG
1.C00A.7:4
REG
1.C01D.6
PCS
BYTE
SYNC
PCS
LANE
ALIGN
IEEE REG
3.1.2
PHY XS
BYTE
SYNC
PHY XS
LANE
ALIGN
IEEE REG
3.1.7
IEEE REG
3.8.11
IEEE REG
3.8.10
See LASI
IEEE REG
3.24.3:0
IEEE REG
3.24.12
IEEE REG
4.1.7
IEEE REG
4.8.11
IEEE REG
4.8.10
See LASI
IEEE REG
4.24.12
IEEE REG
4.1.2
IEEE REG
4.24.3:0
REG
4.C00A.3:0
PHY XS
SIGNAL
DETECT
PMA/PMD
SIGNAL
DETECT
REG
1.C00A.3:0
CX4
SIGNAL_
DETECT
REG
1.C001.10:8
leve
l
REG
3.C001.10:8 level
CX4
LX4
IEEE REG
1.1.2
REG
1.C012h.13
POLARITY
See LASI
FIGURE 4. IEEE AND VENDOR SPECIFIC FAULT AND STATUS REGISTERS (EQUIVALENT SCHEMATIC)
BBT3821
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