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參數(shù)資料
| 型號(hào)： | BBT3821-JH |
| 廠商： | Intersil |
| 文件頁數(shù)： | 49/75頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RE-TIMER OCTAL 192-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 無 |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.1875Gbps |
| 電源電壓： | 1.425 V ~ 2.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應(yīng)商設(shè)備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤 |
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53
JTAG & AC-JTAG Operations
Five pins – TMS, TCK, TDO, TRST, and TDI – support IEEE
Standards 1149.1-2001 JTAG and 1149.6-2003 AC-JTAG
testing. The JTAG test capability has been implemented on
all signal pins. Note that the 1149.1-2001 specification has
removed the previous requirement that the [000...0]
instruction be an entry into EXTEST, and deprecated its use
for anything but a non-test function (e.g. BYPASS). The
BBT3821 fully conforms to this revision. The AC-JTAG test
capability has been implemented on the high-speed
differential output and input terminals. The output
configuration corresponds to Figure 51 in IEEE 1149.6-2003,
except that there is no provision to bring the ‘mission’ signal
into the scan chain, since this 3.125Gbps signal has no
meaningful value at the (asynchronous) JTAG TCK rate, and
the BBT3821 does not support INTEST. The receiver
configuration corresponds to Figure 48, using the DC
detection mode only, according to method 2 of 6.2.3.1 rule
a), and omitting the components needed only for the
unsupported INTEST instruction. The EXTEST_PULSE and
EXTEST_TRAIN instruction timings are illustrated in Figures
37, 38 and 44 while the (DC) EXTEST waveforms are
indicated in Figure 42 in IEEE 1149.6-2003. Provided that
the TCK period is sufficiently longer than the AC-coupling
time constant, controlled by the (external) capacitors and the
input impedance of the BBT3821, (see IEEE 1149.6-2003
clause 6.2.3.1 rule k), the combination of (DC) EXTEST and
EXTEST_PULSE or EXTEST_TRAIN scans can detect
open or shorted capacitors or wires.
The supported boundary scan operation instruction codes
are listed in Table 93:
Note (1): All non-listed codes are also BYPASS.
The Manufacturers ID Code returned when reading the ID
Code from the JTAG pins is as follows:-
V0006351’h
where ‘V’ is an internal 4-bit version number. Consult the
information as to the meaning of the revision number.
Note that the JTAG and AC-JTAG capability is not currently
tested in production.
BIST Operation
In addition to the low, mid and high frequency test patterns
defined in IEEE 802.3ae-2002, which are injected (at the 10-
bit level) directly into the serializers, and controlled via the
page 40 and the “IEEE 10GBASE-X PHY XGXS TEST
CONTROL REGISTER ” on page 47, and to further facilitate
the exercise of all the BT3821 blocks, the device includes a
Built In Self Test (BIST) function. The BIST Data Package
Generator sends out a continuous data stream to emulate
network traffic. The available BIST data patterns are enabled
via the bits in Table 72. The patterns available are:
1. CRPAT pattern per IEEE802.3ae-2002 Annex 48A
2. CJPAT pattern per IEEE802.3ae-2002 Annex 48A
3. A full PRBS23 pattern (223–1 coded bytes, 10 times that
many bits) with nine /K/ “comma” characters as interval
on each XAUI/CX4 lane.
4. A Short Pseudo-Random data pattern (13458 byte long)
with nine /K/ “comma” characters as interval on each
XAUI/CX4 lane.
5. Emulation of an Ethernet Jumbo frame: ||S|| + preamble
+ Random data (4 x 13458 byte long) + ||T|| + IPG;
The ‘PRBS23’-based patterns are derived from a PRBS
generator that, after an Inter-Packet Gap (‘IPG’) of 9 /K/
characters, creates a pseudo-random 223 – 1 byte
sequence. The full sequence is used for the ‘PRBS23’
pattern, while the ‘Short PRBS23’ pattern is truncated after
13458 bytes. Each will start again from the beginning,
repeating indefinitely. This pattern is generated on each
lane, and checked (except for the /K/s, of which one is
required for byte synchronization, but all the others are
ignored) in the same way.
The ‘Jumbo Ethernet Packet’ is similar, except that the
‘Short PRBS23’ pattern is preceded by an /S/ & one
preamble on Lane 0, two preambles on Lanes 1 & 2, and a
preamble and SFD on Lane 3, and followed by a /T/ on lane
0. Apart from providing byte sync (byte alignment), the /K/-
filled IPG allows for lane alignment (using the IDLE-to-
NONIDLE transition alignment engine) and elasticity (by
deleting or adding the requisite number of /K/s). The latter, in
particular, allows one BBT3821 to check the ‘Short PRBS23’
or ‘Jumbo Ethernet Packet’ generated by another BBT3821
running on an independent clock within ±100 ppm. The full
PRBS23 pattern could be over 300 bytes off in one repeat
Table 93. JTAG OPERATIONS
INSTRUCTION
CODE
BYPASS (1)
0000
Sample/Preload
0001
HighZ
0010
Clamp
0011
ID Code
0110
EXTEST
1000
UDR0
1001
EXTEST_PULSE
1011
EXTEST_TRAIN
1100
BYPASS
1111
BBT3821
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