Note (1): The counters do not rollover at FF’h, and are cleared on read. There is also an error flag bit, see register 4.C007, Table 88. Note (" />
參數(shù)資料
型號： BBT3821-JH
廠商： Intersil
文件頁數(shù)： 40/75頁
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標準包裝： 90
類型： 時鐘和數(shù)據(jù)恢復（CDR），多路復用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
45
Note (1): The counters do not rollover at FF’h, and are cleared on read. There is also an error flag bit, see register 4.C007, Table 88.
Note (1): ‘V’ is a version number. See “JTAG & AC-JTAG Operations” on page 53 for a note about the version number.
Note (2): For rows with “A”, the default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92
for details).
Note (3): Read value depends on status signal values. Value shown indicates ‘normal’ operation.
Note (4): The IEEE 802.3ae spec allows this to be all zeroes. A XENPAK (etc.) host can more readily determine where the NVR registers are if this value is zero.
Table 73. BIST ERROR COUNTER REGISTERS
MDIO REGISTER ADDRESSES = 3.49165:6 (3.C00D:E’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
3.49165.15:8
BIST_ERR_CNT_3
Lane 3 errors
00’h
RCNR(1)
Error byte counter of BIST pattern
checker on each Lane
3.49165.7:0
BIST_ERR_CNT_2
Lane 2 errors
00’h
RCNR(1)
3.49166.15:8
BIST_ERR_CNT_1
Lane 1 errors
00’h
RCNR(1)
3.49166.7:0
BIST_ERR_CNT_0
Lane 0 errors
00’h
RCNR(1)
Table 74. MDIO PHY XS DEVAD 4 REGISTERS
PHY XS DEVICE 4 MDIO REGISTERS
ADDRESS
NAME
DESCRIPTION
DEFAULT
AC
(2)
R/W
DETAILS
DEC
HEX
4.0
PHYXS Control 1
Reset, Enable loop back mode.
2040’h
R/W
4.1
PHYXS Status 1
PCS Fault, Link Status
0004’h (3)
RO (LL)
4.2:3
ID Code
Manufacturer and Device OUI
01839C6V’h
RO
See (1)
4.4
Speed Ability
10Gbps Ability
0001’h
RO
4.5
IEEE Devices
Devices in Package, Clause 22 capable
001A’h
RO
4.6
Vendor Devices
Vendor Specific Devices in Pkg
0000’h
RO
4.8
PHYXS Status 2
Device Present, Local Fault, Type Summary 8000’h (3)
RO
4.14:15
4.E:F
Package ID
Package OUI, etc.
00000000’h
RO
See (4)
4.24
4.18
PHYXS Status 3
10GBASE-X PHY XGXS Status
1C0F’h
RO
4.25
4.19
PHYXS Test
10GBASE PHY XS Test Control
0000’h
R/W
4.49152
4.C000
PHYXS Control 2
PHY XS Control Register 2
0F6F’h
A
R/W
4.49153
4.C001
PHYXS Control 3
PHY XS Control Register 3
0800’h
A
R/W
4.49154
4.C002
PHYXS ERR
PHY XS Internal ERROR code register
00FE’h
A
R/W
4.49155
4.C003
PHYXS IDLE
PHY XS Internal IDLE Code Register
0007’h
A
R/W
4.49156
4.C004
PHYXS Loop Back PHY XS Loop Back Control Register
0000’h
A
R/W
4.49157
4.C005
PRE_EMPH
PHY XS Pre-emphasis level
0000’h
A
R/W
4.49158
4.C006
Equalization
PHY XS Equalization Control
0000’h
A
R/W
4.49159
4.C007
Test_Flags
PHY XS Receive Path Test & Status Flags
0000’h
RO LH
4.49160
4.C008
Output Ctrl
Output Control and Test function
AAAA’h
R/W
4.49161
4.C009
Half Rate
Half rate clock mode enable
0000’h
R/W
4.49162
4.C00A
LOS Det
PHY XS Status 4 LOS Register
0000’h
RO LH
4.49163
4.C00B
Reserved
PHY XS Control 4 TXCLK20
0000’h
R/W
4.49167
4.C00F
Soft Reset
Reset (non MDIO)
0000’h
R/W SC
BBT3821
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