Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for d" />
參數(shù)資料
型號(hào)： BBT3821-JH
廠商： Intersil
文件頁(yè)數(shù)： 46/75頁(yè)
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無(wú)
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
50
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): See Note (2) to Table 42 for a note about the equations and symbols used here.
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
register 1.9004’h (see Table 28)
Note (2): See also error counters in registers 3.C00D:E’h (Table 73)
Table 85. PHY XS PRE-EMPHASIS CONTROL
MDIO REGISTER ADDRESS = 4.49157 (4.C005’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49157.15:12
Reserved
4.49157.11:9
PRE_EMP Lane 3
See Table 86 for
settings
0’h
R/W
Configure the level of PHY XS pre-emphasis
(nominal levels indicated)
4.49157.8:6
PRE_EMP Lane 2
0’h
4.49157.5:3
PRE_EMP Lane 1
0’h
4.49157.2:0
PRE_EMP Lane 0
0’h
Table 86. PHY XS XAUI PRE-EMPHASIS CONTROL SETTINGS
ADDRESS
4.C005’h
BITS 2:0
PRE-EMPHASIS (1)
(802.3ak) =
(1-VLOW/VHI)
PRE-EMPHASIS VALUE =
(VHI/ VLOW)-1
ADDRESS 4.C005’h
BITS 2:0
PRE-EMPHASIS
(802.3ak) =
(1-VLOW/VHI)
PRE-EMPHASIS
VALUE =
(VHI/ VLOW)-1
000
0
100
0.50
1.00
001
0.17
0.20
101
0.53
1.28
010
0.28
0.39
110
0.57
1.33
011
0.44
0.79
111
0.60
1.50
Table 87. PHY XS EQUALIZATION CONTROL
MDIO REGISTER ADDRESS = 4.49158 (4.C006’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49158.15:14
Reserved
4.49158.3:0
PHY XS
EQ_COEFF
0’h = no boost in equalizer.
F’h = boost is maximum
0’h
R/W
Configuration of the PHY XS equalizer
Table 88. PHY XS RECEIVE PATH TEST AND STATUS FLAGS
MDIO REGISTER ADDRESS = 4.49159 (4.C007’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.49159.15:12
Test Flags
0’h
ROLH
Special test use only
4.49159.11
EFIFO_3
1 = EFIFO error in Lane
0 = no EFIFO error in
Lane
0’b
ROLH
PHY XS Elasticity FIFO Overflow/Underflow
Error Detection(1)
4.49159.10
EFIFO_2
0’b
4.49159.9
EFIFO_1
0’b
4.49159.8
EFIFO_0
0’b
4.49159.7
Code_3
1 = 10b/8b Code error in
Lane
0 = no 10b/8b Code error
0’b
ROLH
PHY XS 10b/8b Decoder Code Violation
Detection(1)
4.49159.6
Code_2
0’b
4.49159.5
Code_1
0’b
4.49159.4
Code_0
0’b
4.49159.3
BIST_ERR_3
1 = BIST error in lane
0 = No BIST error in lane
0’b
ROLH
Lane by lane BIST error checker indicator(1) (2)
4.49159.2
BIST_ERR_2
0’b
4.49159.1
BIST_ERR_1
0’b
4.49159.0
BIST_ERR_0
0’b
BBT3821
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