Note (1): Active level of these pins is controlled by register 1.49181 (1.C01D’h), see Table 55. If unused, the TX_ENC pin can be tied high, an" />
參數(shù)資料
型號： BBT3821-JH
廠商： Intersil
文件頁數(shù)： 53/75頁
文件大小： 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
57
Note (1): Active level of these pins is controlled by register 1.49181 (1.C01D’h), see Table 55. If unused, the TX_ENC pin can be tied high, and the register bit not
altered. Other unused input pins should be tied low, and the corresponding register bit not altered, so the default value of the register will allow Byte Synch and
cause a ‘No Fault’ indication in the LASI alarm status registers on RESET. See also Table 12, Table 27 and Table 28.
Note (2): Active level of this pin is controlled by register 1.49170 (1.C012’h), see Table 49. Otherwise Note 1 applies.
D9
TX_ENC(1)
Input
Transmit enable input from XENPAK module input “TX ON/OFF”. Controls TX_ENA[3:0].
For normal operation, should be pulled active (default up). 1.2V CMOS
B5
TX_ENA[3] (1)
Output (open drain) Transmit Laser Driver Enables. They are set active only when TX_ENC pin is active and
the corresponding bits in register 1.9 are set low. During RESET stage, these pins are
always low. 1.5V CMOS, 2.5V compatible.
B6
TX_ENA[2] (1)
T5
TX_ENA[1] (1)
R5
TX_ENA[0] (1)
Table 99. MISCELLANEOUS PINS (Continued)
PIN#
NAME
TYPE
DESCRIPTION
Table 100. I2C 2-WIRE SERIAL DATA INTERFACE PINS
PIN#
NAME
TYPE
DESCRIPTION
P9
SDA
I/O (open drain)
I2C Serial Address/Data I/O 1.5V CMOS, 2.5V Tolerant and Compatible
P8
SCL
I/O (open drain)
I2C Serial Interface Clock. 1.5V CMOS, 2.5V Tolerant and Compatible
C7
WRTP
Input
I2C Serial Interface Write Protection. When high, no write to protected
XENPAK basic NVR area is allowed. 1.5V CMOS, 2.5V Tolerant
R6
GPIO[4]
I/O (open drain)
General Purpose I/O Can be used for optical monitoring and status
reporting, and to trigger LASI, or for external control functions. 1.5V CMOS,
2.5V Tolerant and Compatible
P7
GPIO[3]
N7
GPIO[2]
N6
GPIO[1]
P6
GPIO[0]
Table 101. VOLTAGE SUPPLY PINS
PIN#
NAME
TYPE
DESCRIPTION
C6, C13, H13, J4, N5, N13
VDDPR
Supply
2.5V Protection Voltage Supply. May be same level as VDD if no inputs
or outputs go above the VDD level.
A4, A8, A9, A12, A13, B10, N9,
P4, P5
VDD
Supply
1.5V Digital and Core Supply
B4, C4, C14, D4, D13, E4, E13,
F4, F13, G4, G13, K4, K13, L4,
L13, M4, M13, N4, P13, R4, R13,
T4, T13
VDDA
Analog Supply
1.5V Analog Supply. Should be decoupled from VDD
R7, T7
VDDAV
Analog Supply
Analog supply for VCO. Should be decoupled from VDDA
R10, T10
VDDAC
Analog Supply
Analog supply for CMU. Should be decoupled from VDDA
A1, A14, A15, A16, B1, B2, B3,
B8, B13, B16, C1, C9, C11, C15,
C16, D1, D2, D3, D16, E1, E14,
E15, E16, F1, F2, F3, F16, G1,
G14, G15, G16, H1, H2, H3, H4,
H16, J1, J13, J14, J15, J16, K1,
K2, K3, K16, L1, L14, L15, L16,
M1, M2, M3, M16, N1, N14, N15,
N16, P1, P2, P3, P16, R1, R8,
R9, R14, R15, R16, T1, T2, T3,
T6, T16
GNDA
Ground
Ground. Electrically well grounded. Analog and Digital grounds are tied in
the device, but it is recommended that some separation be provided in the
PCB planes outside the device, to minimize the coupling between digital
signals and the analog sections of the device.
BBT3821
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