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參數(shù)資料
| 型號： | BBT3821-JH |
| 廠商： | Intersil |
| 文件頁數(shù)： | 29/75頁 |
| 文件大小： | 0K |
| 描述： | IC RE-TIMER OCTAL 192-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 無 |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.1875Gbps |
| 電源電壓： | 1.425 V ~ 2.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應(yīng)商設(shè)備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤 |
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Note (1): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown first. The value may be overwritten by the Auto-Configure operation
(See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): These bits are latched low on any SIG_DET failure condition detected. They are reset high on being read.
Note (2): These bits are latched high on any LOS condition detected. They are reset low on being read.
Note (1): Default values depend on setting of LX4/CX4 select LX4_MODE pin. LX4 value is shown first. The value may be overwritten by the Auto-Configure operation
(See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): This reset will NOT cause a reload of the NVR or DOM areas, nor an Auto-Configure operation. It will reset the Byte Sync engine, the Lane Alignment engine,
the FIFO pointers, and the I2C controller. The BBT3821 will (if “normally” configured) transmit ||LF|| local fault signals until Byte Sync and Lane Alignment are
re-established, and any DOM update in progress may be aborted.
Table 43. PMA/PMD EQUALIZATION CONTROL
MDIO REGISTER ADDRESS = 1.49158 (1.C006’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
1.49158.15:14
Reserved
1.49158.3:0
PMA EQ_COEFF
0’h = no boost in
equalizer.
F’h = boost is maximum
0’h/C’h
R/W
Configuration of the PMA/PMD equalizer
Table 44. PMA SIG_DET AND LOS DETECTOR STATUS REGISTER
MDIO REGISTER ADDRESS = 1.49162 (1.C00A’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49162.15:8
Reserved
00’b
1.49162.7
SIG_DET_3
1 = CX4 Signal Detect
Asserted
0 = CX4 Signal Detect
Deasserted
1’b
RO/LL(1) Signal Detect for PMA lane 3
1.49162.6
SIG_DET_2
1’b
Signal Detect for PMA lane 2
1.49162.5
SIG_DET_1
1’b
Signal Detect for PMA lane 1
1.49162.4
SIG_DET_0
1’b
Signal Detect for PMA lane 0
1.49162.3
PMA_LOS_3
1 = Signal less than
threshold
0 = Signal greater than
threshold
0’b
RO/LH
(2)
Loss Of Signal for PMA lane 3
1.49162.2
PMA_LOS_2
0’b
Loss Of Signal for PMA lane 2
1.49162.1
PMA_LOS_1
0’b
Loss Of Signal for PMA lane 1
1.49162.0
PMA_LOS_0
0’b
Loss Of Signal for PMA lane 0
Table 45. PMA/PMD MISCELLANEOUS ADJUSTMENT REGISTER
MDIO REGISTER ADDRESS = 1.49163 (1.C00B’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49163.15:10
Reserved
00’h
1.49163.9:6
Amplitude
Output Control (1)
LX4: 5’h
CX4: 3’h
R/W
1.49163.5:2
Pre-emphasis
Fine Control per
lane (1)
LX4: 0’h
CX4: F’h
R/W
Bit 5 is for Lane 3, etc.
1.49163.1:0
Reserved
Internal
00’b
R/W
Test Function, do not alter.
Table 46. PMA/PMD/PCS/PHY XS SOFT RESET REGISTER
MDIO REGISTER ADDRESS = [1,3:4].49167 ([1,3:4].C00F’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49167.15
[3,4].49167.15
SOFT_RESET
Write 1 to initiate.
0’b
R/W SC Reset the entire chip except MDIO register
settings(1)
[1,3:4].49167.14:0
Reserved
BBT3821
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