Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for de" />
參數(shù)資料
型號(hào)： BBT3821-JH
廠商： Intersil
文件頁(yè)數(shù)： 30/75頁(yè)
文件大小： 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無(wú)
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
36
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): If any of these bits is set to ‘1’, it triggers LASI if the corresponding bit in 1.49170.5:0 and the GPIO enable bit 1.36866.3 are set high.
Note (1): If any of these bits is set to ‘1’, it triggers LASI if the corresponding bit in 1.49169.12:8 and the GPIO enable bit 1.36866.3 are set high. The polarity that will
trigger LASI is set by bits 1.49170.12:8 above.
Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Table 47. GPIO PIN DIRECTION CONFIGURE REGISTER
MDIO REGISTER ADDRESS = 1.49168 (1.C010’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49168.15:5
Reserved
1.49168.4:0
GPIO pins
configuration
1 = output
0 = input
00’h(1)
R/W
Controls whether GPIO pin is used as input or
output
Table 48. GPIO PIN INPUT STATUS REGISTER
MDIO REGISTER ADDRESS = 1.49169 (1.C011’h)
BIT
NAME
SETTING
R/W
DESCRIPTION
1.49169.15:13
Reserved
1.49169.12:8
LASI I/P
value
1 = can trigger LASI (1)
0 = cannot trigger LASI
RO/LH
XOR of GPIO Pin I/P and Invert register
1.49170.13:8.
1.49169.7:5
Reserved
1.49169.4:0
GPIO Pin I/P
Value
1 = Pin Hi
0 = Pin Lo
RO
Original values from GPIO pins directly.
Table 49. TX_FAULT & GPIO PIN TO LASI CONFIGURE REGISTER
MDIO REGISTER ADDRESS = 1.49170 (1.C012’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49170.15:14
Reserved
1.49170.13
Invert TX_FAULT 1 = Pin Low,
0 = Pin High to trigger LASI
0’b(2)
R/W
Control Polarity of TX_FAULT pin which will
trigger LASI (if enabled)
1.49170.12:8
Invert LASI I/P
1 = Invert to LASI
0 = Straight to LASI
00’h(2)
R/W
Control XOR of GPIO Pin I/P to LASI I/P
register 1.49169.13:8.
1.49170.7:5
Reserved
1.49170.4:0
Enable LASI I/P
1 = Enable (1)
0 = Do not Enable
00’h(2)
R/W
Enable the GPIO pin value to trigger
GPIO_ALARM to LASI
Table 50. GPIO PIN OUTPUT REGISTER
MDIO REGISTER ADDRESS = 1.49171 (1.C013’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.49171.15:5
Reserved
1.49171.4:0
GPIO Pin
Output
0 = Low
1 = High
00’h(1)
R/W
Controls GPIO pin level if set as output
BBT3821
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