Note (1): See “BIST Operation” on page 53 for a description of these tests and patterns. Note (2): This Short pattern is the f" />
參數(shù)資料
型號： BBT3821-JH
廠商： Intersil
文件頁數(shù)： 39/75頁
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標準包裝： 90
類型： 時鐘和數(shù)據(jù)恢復（CDR），多路復用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應商設備封裝： 192-EBGA-B（17x17）
包裝： 托盤
44
Note (1): See “BIST Operation” on page 53 for a description of these tests and patterns.
Note (2): This Short pattern is the first 13458 Bytes of the full PRBS 223-1 Byte pattern, and also has 9 /K/ per lane as IPG
Note (3): This pattern is an /S/, preamble, the ‘Short PRBS23’ pattern, one /T/, and 9 /K/s, repeated.
Note (4): A Soft Reset is required to activate the newly selected pattern.
Note (5): The checker expects at least one /K/ on each lane between pattern repeats
Table 71. PCS/PHY XS HALF RATE CLOCK CONTROL REGISTER
MDIO REGISTER ADDRESSES = 3.49161 & 4.49161 ([3,4].C009’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
3.49161.15:4
4.49161.15:4
Reserved
0’h
R/W
3.49161.3
4.49161.3
HALF_RATE 3
1’b = half rate clock 0’b = full
rate clock
0’b
R/W
Lane 3 is running at half rate clock speed
3.49161.2
4.49161.2
HALF_RATE 2
1’b = half rate clock 0’b = full
rate clock
0’b
R/W
Lane 2 is running at half rate clock speed
3.49161.1
4.49161.1
HALF_RATE 1
1’b = half rate clock 0’b = full
rate clock
0’b
R/W
Lane 1 is running at half rate clock speed
3.49161.0
4.49161.0
HALF_RATE 0
1’b = half rate clock 0’b = full
rate clock
0’b
R/W
Lane 0 is running at half rate clock speed
Table 72. BIST CONTROL REGISTER
MDIO REGISTER ADDRESS = 3.49164 (3.C00C’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION(1)
3.49164.15
BIST_EN
BIST generator
enable
0’b
R/W
1 = Enable BIST generator
0 = Disable BIST generator
3.49164.14:12
Reserved
3.49164.11
BIST_DIR
Select BIST data output
direction
0’b
R/W
1 = BIST to PCS (transmit path)
0 = BIST to XGXS (receive path)
3.49164.10:8
BIST_PAT
Select BIST
generator data pattern(4)
0’h
R/W
000 = CRPAT
001 = CJPAT
010 = PRBS23 with 9 /K/s as IPG
011 = Short PRBS23 pattern(2)
100 = Jumbo Ethernet packet(3)
Other = reserved
3.49164.7
BIST_DET
BIST checker enable
0’b
R/W
1 = Enable BIST checker
0 = Disable BIST checker
3.49164.6:4
Reserved
3.49164.3
BIST_SRC
Select BIST data checker
input source
0’b
R/W
0 = PCS to BIST (receive path)
1 = XGXS to BIST (transmit path)
3.49164.2:0
BIST_CHK
Select BIST
checker data pattern (5)
0’h
R/W
000 = CRPAT
001 = CJPAT
010 = PRBS23 with /K/’s as IPG
011 = Short PRBS23 pattern(2)
100 = Jumbo Ethernet packet(3)
Other = reserved
BBT3821
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