- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9536 > BBT3821-JH (Intersil)IC RE-TIMER OCTAL 192-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | BBT3821-JH |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 42/75頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RE-TIMER OCTAL 192-BGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 無(wú) |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.1875Gbps |
| 電源電壓： | 1.425 V ~ 2.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應(yīng)商設(shè)備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)當(dāng)前第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)
47
Note (1): The status of these bits depends on the signal conditions. Default shown is for normal operation. The bits contribute to the RX Local Fault bit, see Table 77.
VENDOR-SPECIFIC PHY XS REGISTERS (4.C000’H TO 4.C00B’H)
Table 78. IEEE 10GBASE-X PHY XGXS STATUS REGISTER
MDIO REGISTER ADDRESSES = 4.24 (4.0018’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.24.15:13
Reserved
4.24.12
PHY XS
Lane_Align
1 = 4 Lanes Aligned
0 = Lanes not aligned
1’b(1)
RO
1 = Four 3G receive lanes (on egress path) are
aligned
4.24.11
Test_Pattern
Test Pattern Abilities
1’b
RO
1 = The device is able to generate test patterns for
10GBASE-X
4.24.10
PHYXSLpbk
Loopback Ability
1’b
RO
1 = Device is able to loopback
4.24.9:4
Reserved
4.24.3
Lane3 Sync
1 = Lane is Synchronized
0 = Lane not Synchronized
1’b(1)
RO
Reflects the PCS_SYNC byte alignment state
machine condition; not valid if not enabled in
device (see Table 80)
4.24.2
Lane2 Sync
1’b(1)
RO
4.24.1
Lane1 Sync
1’b(1)
RO
4.24.0
Lane0 Sync
1’b(1)
RO
Table 79. IEEE 10GBASE-X PHY XGXS TEST CONTROL REGISTER
MDIO REGISTER ADDRESS = 4.25 (4.0019’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.25.15:3
Reserved
4.25.2
PHY XS
TestPatEn
Receive Test Pattern
Enable
0’b
R/W
0 = Do not enable Receive test pattern
1 = Enable Receive test pattern
4.25.1:0
PHY XS TestPat
Type
Test pattern select (see
Table 72 for other test
patterns generated by
the BBT3821)
00’b
R/W
11 = Reserved
10 = Mixed frequency test pattern (Continuous /K/ = K28.5)
01 = Low frequency test pattern (repeat 0000011111 = K28.7)
00 = High frequency test pattern (repeat 0101010101 = D10.2)
Table 80. PHY XS CONTROL REGISTER 2
MDIO REGISTER ADDRESS = 4.49152 (4.C000’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49152.15:14
Test Mode
00’b
R/W
User should leave at 00’b
4.49152.13:12
Reserved
4.49152.11
PHY XS Clock
PSYNC
1’b
R/W
1 = Synchronize/align four lanes
0 = Do not synchronize/align four lanes
4.49152.10
PHY XS CODECENA 0 = disable
1 = enable
1’b
R/W
Internal 8B/10B Codec enable/disable
4.49152.9:8
PHY XS CDET[1:0]
Comma Detect
Select.
11’b
R/W
These bits individually enable positive and negative disparity
“comma” detection.
11 = Enable both positive and negative comma detection
10 = Enable positive comma detection only
01 = Enable negative comma detection only
00 = Disable comma detection
4.49152.7
PHY XS
DSKW_SM_EN
0 = disable(2)
1 = enable
0’b
R/W
Enable De-skew state machine control (3) . Forced enabled
by PHY XS XAUI_EN. May not operate correctly unless the
PHY XS PCS_SYNC_EN bit is also set.
4.49152.6:5
PHY XS RCLKMODE 11’b = Local
Reference
Clock(4)
11’b
R/W
Other values should only be used if incoming data is
frequency-synchronous with the local reference clock(4).
BBT3821
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-2NP-IW-B1 | CONVERTER MOD DC/DC 13.8V 100W |
| MS27484E12A35P | CONN PLUG 22POS STRAIGHT W/PINS |
| MAX491CSD | IC TRANS RS485/RS422 14-SOIC |
| VE-2NN-IW-B1 | CONVERTER MOD DC/DC 18.5V 100W |
| IDTQS34X245Q3G | IC BUS SWITCH 32BIT CMOS 80QVSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BBT3821LP-JH | 功能描述:IC RE-TIMER OCTAL 192-BGA RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| BBTEKIT | 功能描述:剝線和切削工具 COMPR AND STRIP TOOL KIT FOR RG59 RG6 CBL RoHS:否 制造商:Molex 產(chǎn)品:Cable Strippers 類型: 描述/功能:Stripper |
| BB-TERM3 | 功能描述:固定接線端子 3-Position Terminal Block Breakout RoHS:否 制造商:Phoenix Contact 產(chǎn)品:Fixed Terminal Blocks 類型:Wire to Board 節(jié)距:5.08 mm 位置/觸點(diǎn)數(shù)量:2 線規(guī)量程:26-16 電流額定值:13.5 A 電壓額定值:250 V 安裝風(fēng)格:Through Hole 安裝角:Straight 端接類型:Screw 觸點(diǎn)電鍍: |
| BB-TG.30.8113 | 功能描述:ANT LTE, TERMINAL 制造商:b&b smartworx, inc. 系列:- 零件狀態(tài):在售 配件類型:天線 配套使用產(chǎn)品/相關(guān)產(chǎn)品:- 標(biāo)準(zhǔn)包裝:1 |
| BBU-03 | 制造商:Highpoint Technology 功能描述:BATTERY BACK UP - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。