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參數(shù)資料
| 型號： | BBT3821-JH |
| 廠商： | Intersil |
| 文件頁數(shù)： | 43/75頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RE-TIMER OCTAL 192-BGA |
| 標準包裝： | 90 |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 無 |
| 輸入： | CML |
| 輸出： | CML，CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 8:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.1875Gbps |
| 電源電壓： | 1.425 V ~ 2.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 192-EBGA |
| 供應商設備封裝： | 192-EBGA-B（17x17） |
| 包裝： | 托盤 |
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48
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (3): These state machines are implemented according to 802.3ae-2002 clause 48.
Note (4): If the RCLKMODE bits are set to 10’b, the internal XGMII clock from the PHY XS to the PCS is set to the recovered clock. If the PHY XS Clock PSYNC bit is set (the
default), the recovered clock from Lane 0 is used for all four lanes, if cleared, or if the RCLKMODE bits are set to 01’b or 00’b, each lane uses its own recovered clock.
If the incoming data is NOT frequency-synchronous with the local reference clock, data will be corrupted (occasional characters will be lost, or repeated).
Note (5): This bit name reflects the “embedded” PCS function within an XGXS, see IEEE 802.3 Clause 47.2.1.
4.49152.4
PHY XS
PCS_SYNC_EN(5)
0 = disable(2)
1 = enable
0’b
R/W
Enable 8b/10b PCS coding synchronized state machine(3) to
control the byte alignment (IEEE ‘code-group alignment’) of
the high speed de-serializer
4.49152.3
PHY XS IDLE_D_EN
1 = enable
0 = disable
1’b
R/W
Enables IDLE vs. NON-IDLE detection for lane alignment.
Overridden by PHY XS XAUI_EN, see Table 88
4.49152.2
PHY XS ELST_EN
1 = enable
0 = disable
1’b
R/W
Enable the elastic function of the PHY XS receiver buffer
4.49152.1
PHY XS
A_ALIGN_DIS
1 = disable(2)
0 = enable
1’b
R/W
PHY XS Receiver aligns data on incoming “/A/” characters
(K28.3). If disabled (default), receiver aligns data on IDLE to
non-IDLE transitions (if bit 3 set). Overridden by PHY XS
XAUI_EN, see Table 81
4.49152.0
PHY XS CAL_EN
1 = enable
0 = disable
1’b
R/W
Enable de-skew calculator of PHY XS receiver Align FIFO
Table 80. PHY XS CONTROL REGISTER 2 (Continued)
MDIO REGISTER ADDRESS = 4.49152 (4.C000’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
Table 81. PHY XS CONTROL REGISTER 3
MDIO REGISTER ADDRESS = 4.49153 (4.C001’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49153.15
PHY XS DC_O_DIS 1 = Disable, 0 = normal
0’b
R/W
PHY XS DC Offset Disable
4.49153.14:13
Reserved
4.49153.12
MF_SEL
Select source of signals
for four MF pins
0’b
R/W
1 = Select signals from PMA/PCS
to be output on MF pins
0 = Select signals from PHY
XGXS to be output on MF pins
4.49153.11
PHY XS XAUI_EN
1 = enable
0 = disable
1’b
R/W
Enables all XAUI features per 802.3ae-2002. It is
equivalent to setting the configuration bits listed in
Table 65 (but does not change the actual value of the
corresponding MDIO registers’ bits).
4.49153.10:8
PHY_LOS_TH
0’h = 160mVp-p
1’h = 240mVp-p
2’h = 200mVp-p
3’h = 120mVp-p
4’h = 80mVp-p
else = 160mVp-p
000’b
R/W
Set the threshold voltage for the Loss Of Signal
(LOS) detection circuit in PHY XS. Nominal levels are
listed for each control value. Note that the differential
peak-to-peak value is twice that listed
4.49153.7
Reserved
4.49153.6
PHY XS
AKR_SM_EN
1 = enable random A/K/R
0 = /K/ only(2)
0’b
R/W
Enable pseudo- random A/K/R(3) in Inter Packet Gap
(IPG) on transmitter side (vs. /K/ only)
4.49153.5
PHY XS TRANS_EN 1 = enable
0 = disable(2)
Overridden by PHY XS
XAUI_EN, see Table 65
0’b
R/W
This bit enables the transceiver to translate an “IDLE”
pattern in the internal FIFOs (matching the value of
register 4.C003’h) to and from the XAUI IDLE /K/
comma character or /A/, /K/ & /R/ characters.
4.49153.4
Reserved
4.49153.3
PHY XS TX_SDR
PHY XS receive
data rate
0’b
R/W
1 = PHY XS takes data from PCS at half speed
0 = PHY XS takes data from PCS at full speed
BBT3821
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