Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for d" />
參數(shù)資料
型號： BBT3821-JH
廠商： Intersil
文件頁數(shù)： 44/75頁
文件大小： 0K
描述： IC RE-TIMER OCTAL 192-BGA
標準包裝： 90
類型： 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤
49
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden by PHY XS XAUI_EN, see also Table 65.
Note (3): This state machine is implemented according toIEEE 802.3ae-2002 clause 48.
Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (2): These bits are overridden to FE’h by PHY XS XAUI_EN, see Table 65 and Table 81.
Note (1): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): Loopback is from XAUI Serial I/P to Serial O/P. Recommended use for test purposes only; no retiming or pre-emphasis is performed
Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
4.49153.2:0
MF_CTRL
0 = BIST_ERR
1 = LOS
2,3 = Reserved
4 = TXFIFO_ERR
5 = AFIFO_ERR
6 = EFIFO_ERR
000’b
R/W
Control the meaning of Multi-function pins MF[3:0] of
the 4 lanes in the device selected by MF_SEL above
(bit 12)
Table 81. PHY XS CONTROL REGISTER 3 (Continued)
MDIO REGISTER ADDRESS = 4.49153 (4.C001’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
Table 82. PHY XS INTERNAL ERROR CODE REGISTER
MDIO REGISTER, ADDRESS = 4.49154 (4.C002’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49154.15:8
Reserved
4.49154.7:0
PHY XS
ERROR
Desired Value(2)
FE’h
R/W
Error Code. These bits allow the internal FIFO
ERROR control character to be programmed.
Table 83. PHY XS INTERNAL IDLE CODE REGISTER
MDIO REGISTER ADDRESS = 4.49155 (4.C003’h)
BIT
NAME
SETTING
DEFAULT(1)
R/W
DESCRIPTION
4.49155.15:8
Reserved
4.49155.7:0
PHY XS
XG_IDLE
Desired Value
07’h
R/W
IDLE pattern in internal FIFOs for translation
to/from XAUI IDLEs
Table 84. PHY XS MISCELLANEOUS LOOP BACK CONTROL REGISTER
MDIO REGISTER ADDRESS = 4.49156 (4.C004’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
4.49156.15:13
Reserved
4.49156.12
Test LP
1 = enable
0’b(1)
R/W
Serial Host Test Loopback
4.49156.11
SLP_3
1 = enable PHY XS
Network Loopback
0 = disable
0’b(2)
R/W
Internal PHY XS Serial Loop Back Enable for each
individual lane. When high, it routes the internal
XAUI Serial output to the Serial input.
4.49156.10
SLP_2
0’b(2)
4.49156.9
SLP_1
0’b(2)
4.49156.8
SLP_0
0’b(2)
4.49156.7:4
Reserved
4.49156.3
PLP_3
1 = enable System (“PCS”)
Parallel Loopback
0 = disable
0’b(2)
R/W
PCS Parallel Loop Back Enable for each individual
lane. When high, it routes the XAUI Serial input to
the Serial output via the full PHY XS.
4.49156.2
PLP_2
0’b(2)
4.49156.1
PLP_1
0’b(2)
4.49156.0
PLP_0
0’b(2)
BBT3821
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