under these circumstances, greatly exceeding the elasticity FIFO’s range, unless the clocks were synchronized. The CJPAT and CRPAT patterns are" />
參數(shù)資料
型號(hào)： BBT3821-JH
廠商： Intersil
文件頁(yè)數(shù)： 50/75頁(yè)
文件大?。?/td> 0K
描述： IC RE-TIMER OCTAL 192-BGA
標(biāo)準(zhǔn)包裝： 90
類(lèi)型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器
PLL： 無(wú)
輸入： CML
輸出： CML，CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 8:8
差分 - 輸入:輸出： 是/是
頻率 - 最大： 3.1875Gbps
電源電壓： 1.425 V ~ 2.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 192-EBGA
供應(yīng)商設(shè)備封裝： 192-EBGA-B（17x17）
包裝： 托盤(pán)
54
under these circumstances, greatly exceeding the elasticity
FIFO’s range, unless the clocks were synchronized. The
CJPAT and CRPAT patterns are those defined by IEEE
802.3ae-2002 Annex 48.
Either the BIST_EN bit (see Table 72 or the BIST_ENA pin
(see Table 99 on Page 56) will cause the Serial Transmitter
selected by the BIST_DIR bit to put out the pattern selected
by the BIST_PAT bits (see Table 72). The BIST_DET bit will
enable the Serial Receiver selected by the BIST_SRC bit to
search its incoming bit stream for the pattern (separately)
selected by the BIST_CHK bits (see Table 72). Once the
comma group or IPG has set the byte alignment, the BIST
error detector will be enabled, and the decoded pattern will
be then be checked. Any bit error will set the error detector
for the corresponding lane, and increment the
BIST_ERR_CNT counters (see Table 73). These detectors
may be monitored via the MF[3:0] pins (see Table 99) and
both they and the counters may be read via the MDIO
system (see Table 81).
The separate setup for BIST generation and checking
means that two BBT3821s may be tested with a different
pattern in each direction on the link between them.
The signal flows provided for these BIST patterns are shown
in Figure 6. The generator output may be injected (in place
of the ‘normal’ signal flow) into the AKR Randomizer in either
the PCS or PHY XS, as controlled by the "BIST CONTROL
REGISTER" (see Table 72). The signal may be looped back
using the PMA or PHY XS loopbacks (respectively), and
checked at the output of the respective Elastic FIFO, or
continue on to the other loopback, and checked at the output
of the other Elastic FIFO. The internal loopback(s) may be
replaced by external loopbacks, and in each ‘full loop’ case
this will test virtually the complete device; if both possible full
loops are checked, both complete signal paths are tested.
Note that if any external loopback changes the clock
domain, the full ‘PRBS23’ pattern cannot be checked.
PCS //
= PHY XS
Loopback
4.C004 &
~3.0.14)
PCS // Network
Loopback (3.C004)
CDR
Des
e
ria
liz
e
r&
Co
mm
aDete
ctor
10B/8B
Decoder
RX FIFO
Deskew
S
e
rial
iz
er
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
TXPn P/N
RCXn P/N
Equalizer
Signal
Detect
CDR
D
es
eri
al
iz
er
&
Co
m
aD
ete
ct
or
10B/8B
Decoder
RX FIFO
Deskew
Se
ria
liz
er
8B/10B
Encoder,
AKR
Generator
TXFIFO &
Error and
Orderset
Detector
RXPnP/N
Equalizer
Signal
Detect
TCXn P/N
PMA
Loopback
(1.0.14 &
1.C004)
PHY XS
(Serial)
Loopback
(4.0.14 &
4.C004)
Ingress
Egress
Ingress
Egress
HF, LF, MixedF
Generator
HF, LF, MixedF
Generator
CRPAT, CJPAT,
PRBS23
Checker
CRPAT, CJPAT,
PRBS23
Generater
IEEE REG
4.25
IEEE REG
3.25
Vendor
REG
3.C003
Vendor
REG
3.C003
Device Address 3 PCS
Device Address 4 PHY XGXS
Device Address 1 PMA/PMD
O
nl
yO
ne
La
ne
of
F
o
ur
Sh
ow
n
O
nly
One
La
ne
of
Fo
ur
S
ho
w
n
FIGURE 6. BLOCK DIAGRAM OF BIST OPERATION
BBT3821
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