參數(shù)資料
型號： EP2C20F256I6N
廠商： ALTERA CORP
元件分類： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封裝： LEAD FREE, FBGA-256
文件頁數(shù)： 131/168頁
文件大?。?/td> 2206K
代理商： EP2C20F256I6N
Altera Corporation
2–53
February 2007
Cyclone II Device Handbook, Volume 1
Cyclone II Architecture
f
For more information on Cyclone II supported I/O standards, see the
Selectable I/O Standards in Cyclone II Devices chapter in Volume 1 of the
Cyclone II Device Handbook.
High-Speed Differential Interfaces
Cyclone II devices can transmit and receive data through LVDS signals at
a data rate of up to 640 Mbps and 805 Mbps, respectively. For the LVDS
transmitter and receiver, the Cyclone II device’s input and output pins
support serialization and deserialization through internal logic.
Differential HSTL-15 class I
or class II
Pseudo
differential (4)
1.5 V
v (7)
1.5 V
v
v
Differential HSTL-18 class I
or class II
Pseudo
differential (4)
1.8 V
v (7)
1.8 V
v
v
LVDS
Differential
2.5 V
vvv
v
RSDS and mini-LVDS (8)
Differential
2.5 V
vv
v
LVPECL (9)
Differential
3.3 V/
2.5 V/
1.8 V/
1.5 V
vv
Notes to Table 2–17:
(1)
To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and turn on the Allow
LVTTL and LVCMOS input levels to overdrive input buffer
option in the Quartus II software.
(2)
These pins support SSTL-18 class II and 1.8- and 1.5-V HSTL class II inputs.
(3)
PCI-X does not meet the IV curve requirement at the linear region. PCI-clamp diode is not available on top and
bottom I/O pins.
(4)
Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed
as inverted. Pseudo-differential HSTL and SSTL inputs treat differential inputs as two single-ended HSTL and
SSTL inputs and only decode one of them.
(5)
This I/O standard is not supported on these I/O pins.
(6)
This I/O standard is only supported on the dedicated clock pins.
(7)
PLL_OUT does not support differential SSTL-18 class II and differential 1.8 and 1.5-V HSTL class II.
(8)
mini-LVDS and RSDS are only supported on output pins.
(9)
LVPECL is only supported on clock inputs.
Table 2–17. Cyclone II Supported I/O Standards & Constraints (Part 2 of 2)
I/O Standard
Type
VCCIO Level
Top & Bottom
I/O Pins
Side I/O Pins
Input
Output
CLK,
DQS
User I/O
Pins
CLK,
DQS
PLL_OUT
User I/O
Pins
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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