參數(shù)資料
型號： EP2C20F256I6N
廠商： ALTERA CORP
元件分類： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封裝： LEAD FREE, FBGA-256
文件頁數(shù)： 60/168頁
文件大?。?/td> 2206K
代理商： EP2C20F256I6N
5–62
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2008
Timing Specifications
tFALL
80–20%
150
200
250
150
200
250
150
200
250 (11)
ps
tLOCK
——
—
100
——
100
——
100 (12)
μs
Notes to Table 5–50:
(1)
The maximum data rate that complies with duty cycle distortion of 45–55%.
(2)
The maximum data rate when taking duty cycle in absolute ps into consideration that may not comply with 45–55%
duty cycle distortion. If the downstream receiver can handle duty cycle distortion beyond the 45–55% range, you
may use the higher data rate values from this column. You can calculate the duty cycle distortion as a percentage
using the absolute ps value. For example, for a data rate of 640 Mbps (UI = 1562.5 ps) and a tDUTY of 250 ps, the
duty cycle distortion is ± tDUTY/(UI*2) *100% = ± 250 ps/(1562.5 *2) * 100% = ± 8%, which gives you a duty cycle
distortion of 42–58%.
(3)
The TCCS specification applies to the entire bank of LVDS, as long as the SERDES logic is placed within the LAB
adjacent to the output pins.
(4)
For extended temperature devices, the maximum input clock frequency for ×10 through ×2 modes is 137.5 MHz.
(5)
For extended temperature devices, the maximum data rate for ×10 through ×2 modes is 275 Mbps.
(6)
For extended temperature devices, the maximum input clock frequency for ×10 through ×2 modes is 200 MHz.
(7)
For extended temperature devices, the maximum data rate for ×10 through ×2 modes is 400 Mbps.
(8)
For extended temperature devices, the maximum input clock frequency for ×1 mode is 340 MHz.
(9)
For extended temperature devices, the maximum data rate for ×1 mode is 340 Mbps.
(10) For extended temperature devices, the maximum output jitter (peak to peak) is 600 ps.
(11) For extended temperature devices, the maximum tRISE and tFALL are 300 ps.
(12) For extended temperature devices, the maximum lock time is 500 us.
Table 5–50. LVDS Transmitter Timing Specification (Part 2 of 2)
Symbol
Conditions
–6 Speed Grade
–7 Speed Grade
–8 Speed Grade
Unit
Min
Typ
Max
(1)
Max
(2)
Min
Typ
Max
(1)
Max
(2)
Min
Typ
Max
(1)
Max
(2)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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