參數(shù)資料
型號: EP2C20F256I6N
廠商: ALTERA CORP
元件分類: FPGA
英文描述: FPGA, 1196 CLBS, PBGA256
封裝: LEAD FREE, FBGA-256
文件頁數(shù): 53/168頁
文件大?。?/td> 2206K
代理商: EP2C20F256I6N
5–56
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2008
Timing Specifications
Figure 5–3. High-Speed I/O Timing Diagram
Figure 5–4 shows the high-speed I/O timing budget.
Sampling window
SW
The period of time during which the data must be valid in order for you
to capture it correctly. Sampling window is the sum of the setup time,
hold time, and jitter. The window of tSU + tH is expected to be centered
in the sampling window.
SW = TUI – TCCS – (2 × RSKM)
Receiver input skew
margin
RSKM
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2
Input jitter (peak to peak)
Peak-to-peak input jitter on high-speed PLLs.
Output jitter (peak to peak)
Peak-to-peak output jitter on high-speed PLLs.
Signal rise time
tRISE
Low-to-high transmission time.
Signal fall time
tFAL L
High-to-low transmission time.
Lock time
tLOCK
Lock time for high-speed transmitter and receiver PLLs.
Table 5–47. High-Speed I/O Timing Definitions (Part 2 of 2)
Parameter
Symbol
Description
Sampling Window (SW)
Time Unit Interval (TUI)
RSKM
TCCS
RSKM
TCCS
Internal Clock
External
Input Clock
Receiver
Input Data
相關PDF資料
PDF描述
EP2SGX60CF780C3N FPGA, 60440 CLBS, 717 MHz, PBGA780
EP2SGX60CF780C3 FPGA, 60440 CLBS, 717 MHz, PBGA780
EP2SGX60CF780C4N FPGA, 60440 CLBS, 717 MHz, PBGA780
EP2SGX60CF780C4 FPGA, 60440 CLBS, 717 MHz, PBGA780
EP2SGX60CF780C5N FPGA, 60440 CLBS, 640 MHz, PBGA780
相關代理商/技術參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256