參數(shù)資料
    

    


    


    
型號(hào)：
EP2C20F256I6N

    

    
廠商：
ALTERA CORP

    

    
元件分類：
FPGA

    

    
英文描述：
FPGA, 1196 CLBS, PBGA256

    

    
封裝：
LEAD FREE, FBGA-256

    

    
文件頁數(shù)：
138/168頁

    

    
文件大?。?/td>
2206K

    

    
代理商：
EP2C20F256I6N


    

    

    

	
    
    
    

    
    
	
    Altera Corporation
    2–59
    February 2007
    Cyclone II Device Handbook, Volume 1
    Cyclone II Architecture
    Figure 2–29. EP2C15, EP2C20, EP2C35, EP2C50 & EP2C70 I/O Banks
    (1)
    This is a top view of the silicon die.
    (2)
    This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
    (3)
    The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output
    pins.
    (4)
    The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock
    pins.
    (5)
    The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock
    pins.
    Each I/O bank has its own VCCIO pins. A single device can support
    1.5-V, 1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support
    a different standard with different I/O voltages. Each bank also has
    dual-purpose VREF pins to support any one of the voltage-referenced
    I/O Bank 2
    Regular I/O Block
    Bank 8
    Regular I/O Block
    Bank 7
    I/O Bank 3
    I/O Bank 4
    I/O Bank 1
    I/O Bank 5
    I/O Bank 6
    Individual
    Power Bus
    All I/O Banks Support
    ■ 3.3-V LVTTL/LVCMOS
    ■ 2.5-V LVTTL/LVCMOS
    ■ 1.8-V LVTTL/LVCMOS
    ■ 1.5-V LVCMOS
    ■ LVDS
    ■ RSDS
    ■ mini-LVDS
    ■ LVPECL (3)
    ■ SSTL-2 Class I and II
    ■ SSTL-18 Class I
    ■ HSTL-18 Class I
    ■ HSTL-15 Class I
    ■ Differential SSTL-2 (4)
    ■ Differential SSTL-18 (4)
    ■ Differential HSTL-18 (5)
    ■ Differential HSTL-15 (5)
    I/O Banks 3 & 4 Also Support
    the SSTL-18 Class II,
    HSTL-18 Class II, & HSTL-15
    Class II I/O Standards
    I/O Banks 7 & 8 Also Support
    the SSTL-18 Class II,
    HSTL-18 Class II, & HSTL-15
    Class II I/O Standards
    I/O Banks 5 & 6 Also
    Support the 3.3-V PCI
    & PCI-X I/O Standards
    I/O Banks 1 & 2 Also
    Support the 3.3-V PCI
    & PCI-X I/O Standards
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
EP2C20F256I8
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP2C20F256I8GA
 制造商:Altera Corporation 功能描述:

    

    
EP2C20F256I8N
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP2C20F484C6
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
EP2C20F484C6N
功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs
 RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256

    

    
    
    
    
	
    	
    
    
     
     
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