參數(shù)資料
型號： EP2C20F256I6N
廠商： ALTERA CORP
元件分類： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封裝： LEAD FREE, FBGA-256
文件頁數(shù)： 95/168頁
文件大小： 2206K
代理商： EP2C20F256I6N
2–20
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
Global Clock Network & Phase-Locked Loops
Dedicated Clock Pins
Larger Cyclone II devices (EP2C15 and larger devices) have 16 dedicated
clock pins (CLK[15..0], four pins on each side of the device). Smaller
Cyclone II devices (EP2C5 and EP2C8 devices) have eight dedicated clock
pins (CLK[7..0], four pins on left and right sides of the device). These
CLK pins drive the global clock network (GCLK), as shown in
If the dedicated clock pins are not used to feed the global clock networks,
they can be used as general-purpose input pins to feed the logic array
using the MultiTrack interconnect. However, if they are used as general-
purpose input pins, they do not have support for an I/O register and
must use LE-based registers in place of an I/O register.
Dual-Purpose Clock Pins
Cyclone II devices have either 20 dual-purpose clock pins,
DPCLK[19..0]
or 8 dual-purpose clock pins, DPCLK[7..0]. In the
larger Cyclone II devices (EP2C15 devices and higher), there are
20 DPCLK pins; four on the left and right sides and six on the top and
bottom of the device. The corner CDPCLK pins are first multiplexed before
they drive into the clock control block. Since the signals pass through a
multiplexer before feeding the clock control block, these signals incur
more delay to the clock control block than other DPCLK pins that directly
feed the clock control block. In the smaller Cyclone II devices (EP2C5 and
EP2C8 devices), there are eight DPCLK pins; two on each side of the device
A programmable delay chain is available from the DPCLK pin to its fan-
out destinations. To set the propagation delay from the DPCLK pin to its
fan-out destinations, use the Input Delay from Dual-Purpose Clock Pin
to Fan-Out Destinations
assignment in the Quartus II software.
These dual-purpose pins can connect to the global clock network for
high-fanout control signals such as clocks, asynchronous clears, presets,
and clock enables, or protocol control signals such as TRDY and IRDY for
PCI, or DQS signals for external memory interfaces.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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