參數(shù)資料
型號： EP2C20F256I6N
廠商： ALTERA CORP
元件分類： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封裝： LEAD FREE, FBGA-256
文件頁數(shù)： 25/168頁
文件大?。?/td> 2206K
代理商： EP2C20F256I6N
5–30
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2008
Timing Specifications
IOE Programmable Delay
Refer to Table 5–36 and 5–37 for IOE programmable delay.
Table 5–36. Cyclone II IOE Programmable Delay on Column Pins Notes (1), (2)
Parameter Paths Affected
Number
of
Settings
Fast Corner
–6 Speed
Grade
–7 Speed
Grade
–8 Speed
Grade
Unit
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Input Delay
from Pin to
Internal
Cells
Pad -> I/O
dataout to core
7
0
2233
0
3827
0
4232
0
4349
ps
0
2344
—
0
4088
—
ps
Input Delay
from Pin to
Input
Register
Pad -> I/O
input register
8
0
2656
0
4555
0
4914
0
4940
ps
0
2788
—
0
4748
—
ps
Delay from
Output
Register to
Output Pin
I/O output
register -> Pad
2
0
303
0
563
0
638
0
670
ps
0
318
—
0
617
—
ps
Notes to Table 5–36:
(1)
The incremental values for the settings are generally linear. For exact values of each setting, use the latest version
of the Quartus II software.
(2)
The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II
software.
(3)
The value in the first row for each parameter represents the fast corner timing parameter for industrial and
automotive devices. The second row represents the fast corner timing parameter for commercial devices.
(4)
The value in the first row is for automotive devices. The second row is for commercial devices.
Table 5–37. Cyclone II IOE Programmable Delay on Row Pins Notes (1), (2) (Part 1 of 2)
Parameter
Paths
Affected
Number
of
Settings
Fast Corner (3)
–6 Speed
Grade
–7 Speed
Grade (4)
–8 Speed Grade
Unit
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Input Delay
from Pin to
Internal
Cells
Pad ->
I/O
dataout
to core
7
0
2240
0
3776
0
4174
0
4290
ps
0
2352
—
0
4033
—
ps
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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