參數(shù)資料
型號： EP2C20F256I6N
廠商： ALTERA CORP
元件分類： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封裝： LEAD FREE, FBGA-256
文件頁數(shù)： 148/168頁
文件大?。?/td> 2206K
代理商： EP2C20F256I6N
3–6
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
Configuration Schemes
SRAM configuration elements allow Cyclone II devices to be
reconfigured in-circuit by loading new configuration data into the device.
With real-time reconfiguration, the device is forced into command mode
with the
nCONFIG pin. The configuration process loads different
configuration data, reinitializes the device, and resumes user-mode
operation. You can perform in-field upgrades by distributing new
configuration files within the system or remotely.
A built-in weak pull-up resistor pulls all user I/O pins to VCCIO before
and during device configuration.
The configuration pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O
standards. The voltage level of the configuration output pins is
determined by the VCCIO of the bank where the pins reside. The bank
VCCIO selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Configuration
Schemes
You can load the configuration data for a Cyclone II device with one of
three configuration schemes (see Table 3–4), chosen on the basis of the
target application. You can use a configuration device, intelligent
controller, or the JTAG port to configure a Cyclone II device. A low-cost
configuration device can automatically configure a Cyclone II device at
system power-up.
Multiple Cyclone II devices can be configured in any of the three
configuration schemes by connecting the configuration enable (
nCE) and
configuration enable output (
nCEO) pins on each device.
f
For more information on configuration, see the Configuring Cyclone II
Devices chapter of the Cyclone II Handbook, Volume 2.
Table 3–4. Data Sources for Configuration
Configuration
Scheme
Data Source
Active serial (AS)
Low-cost serial configuration device
Passive serial (PS) Enhanced or EPC2 configuration device, MasterBlaster, ByteBlasterMV, ByteBlaster II or
USB Blaster download cable, or serial data source
JTAG
MasterBlaster, ByteBlasterMV, ByteBlaster II or USB Blaster download cable or a
microprocessor with a Jam or JBC file
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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