參數(shù)資料
型號： EP2C20F256I6N
廠商： ALTERA CORP
元件分類： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封裝： LEAD FREE, FBGA-256
文件頁數(shù)： 163/168頁
文件大?。?/td> 2206K
代理商： EP2C20F256I6N
5–4
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2008
Operating Conditions
Table 5–4 shows the maximum VIN overshoot voltage and the
dependency on the duty cycle of the input signal. Refer to Table 5–3 for
more information.
RCONF (5) (6)
Value of I/O pin
pull-up resistor
before and during
configuration
VIN = 0 V; VCCIO = 3.3 V
10
25
50
k
Ω
VIN = 0 V; VCCIO = 2.5 V
15
35
70
k
Ω
VIN = 0 V; VCCIO = 1.8 V
30
50
100
k
Ω
VIN = 0 V; VCCIO = 1.5 V
40
75
150
k
Ω
VIN = 0 V; VCCIO = 1.2 V
50
90
170
k
Ω
Recommended
value of I/O pin
external pull-down
resistor before and
during configuration
—1
2
k
Ω
Notes to Table 5–3:
(1)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(2)
The minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the
voltages shown in Table 5–4, based on input duty cycle for input currents less than 100 mA. The overshoot is
dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.
(3)
This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(4)
Maximum values depend on the actual TJ and design utilization. See the Excel-based PowerPlay Early Power
Estimator (www.altera.com) or the Quartus II PowerPlay Power Analyzer feature for maximum values. Refer to
(5)
RCONF values are based on characterization. RCONF = VCCIO/IRCONF. RCONF values may be different if VIN value is
not 0 V. Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
(6)
Minimum condition at –40°C and high VCC, typical condition at 25°C and nominal VCC and maximum condition at
125°C and low VCC for RCONF values.
(7)
These values apply to all VCCIO settings.
Table 5–3. DC Characteristics for User I/O, Dual-Purpose, and Dedicated Pins (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Unit
Table 5–4. VIN Overshoot Voltage for All Input Buffers
Maximum VIN (V)
Input Signal Duty Cycle
4.0
100% (DC)
4.1
90%
4.2
50%
4.3
30%
4.4
17%
4.5
10%
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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