參數(shù)資料
型號(hào)： EP2C20F256I6N
廠商： ALTERA CORP
元件分類： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封裝： LEAD FREE, FBGA-256
文件頁數(shù)： 149/168頁
文件大?。?/td> 2206K
代理商： EP2C20F256I6N
Altera Corporation
3–7
February 2007
Cyclone II Device Handbook, Volume 1
Configuration & Testing
Cyclone II
Automated
Single Event
Upset Detection
Cyclone II devices offer on-chip circuitry for automated checking of
single event upset (SEU) detection. Some applications that require the
device to operate error free at high elevations or in close proximity to
earth’s North or South Pole require periodic checks to ensure continued
data integrity. The error detection cyclic redundancy code (CRC) feature
controlled by the Device & Pin Options dialog box in the Quartus II
software uses a 32-bit CRC circuit to ensure data reliability and is one of
the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Cyclone II devices, eliminating the need for external logic. For
Cyclone II devices, the CRC is pre-computed by Quartus II software and
then sent to the device as part of the POF file header. The
CRC_ERROR pin
reports a soft error when configuration SRAM data is corrupted,
indicating to the user to preform a device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry in the Cyclone II devices performs error detection
automatically. This error detection circuitry in Cyclone II devices
constantly checks for errors in the configuration SRAM cells while the
device is in user mode. You can monitor one external pin for the error and
use it to trigger a re-configuration cycle. You can select the desired time
between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC checker between 400 kHz to 80 MHz. This
controls the rate that the CRC circuitry verifies the internal configuration
SRAM bits in the FPGA device.
f
For more information on CRC, refer to AN: 357 Error Detection Using CRC
in Altera FPGAs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP2C20F256I8 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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