- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295887 > EP2C20F256I6N (ALTERA CORP) FPGA, 1196 CLBS, PBGA256 PDF資料下載
參數(shù)資料
| 型號(hào)： | EP2C20F256I6N |
| 廠商： | ALTERA CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1196 CLBS, PBGA256 |
| 封裝： | LEAD FREE, FBGA-256 |
| 文件頁(yè)數(shù)： | 68/168頁(yè) |
| 文件大?。?/td> | 2206K |
| 代理商： | EP2C20F256I6N |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)當(dāng)前第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)
2–4
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
Logic Elements
Another special packing mode allows the register output to feed back into
the LUT of the same LE so that the register is packed with its own fan-out
LUT, providing another mechanism for improved fitting. The LE can also
drive out registered and unregistered versions of the LUT output.
In addition to the three general routing outputs, the LEs within an LAB
have register chain outputs. Register chain outputs allow registers within
the same LAB to cascade together. The register chain output allows an
LAB to use LUTs for a single combinational function and the registers to
be used for an unrelated shift register implementation. These resources
speed up connections between LABs while saving local interconnect
resources. See “MultiTrack Interconnect” on page 2–10 for more
information on register chain connections.
LE Operating Modes
The Cyclone II LE operates in one of the following modes:
■
Normal mode
■
Arithmetic mode
Each mode uses LE resources differently. In each mode, six available
inputs to the LE—the four data inputs from the LAB local interconnect,
the LAB carry-in from the previous carry-chain LAB, and the register
chain connection—are directed to different destinations to implement the
desired logic function. LAB-wide signals provide clock, asynchronous
clear, synchronous clear, synchronous load, and clock enable control for
the register. These LAB-wide signals are available in all LE modes.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which LE operating mode to
use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinational functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see Figure 2–3). The
Quartus II Compiler automatically selects the carry-in or the data3
signal as one of the inputs to the LUT. LEs in normal mode support
packed registers and register feedback.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP2SGX60CF780C3N | FPGA, 60440 CLBS, 717 MHz, PBGA780 |
| EP2SGX60CF780C3 | FPGA, 60440 CLBS, 717 MHz, PBGA780 |
| EP2SGX60CF780C4N | FPGA, 60440 CLBS, 717 MHz, PBGA780 |
| EP2SGX60CF780C4 | FPGA, 60440 CLBS, 717 MHz, PBGA780 |
| EP2SGX60CF780C5N | FPGA, 60440 CLBS, 640 MHz, PBGA780 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP2C20F256I8 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2C20F256I8GA | 制造商:Altera Corporation 功能描述: |
| EP2C20F256I8N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2C20F484C6 | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP2C20F484C6N | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。