參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內(nèi)存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 107/139頁
文件大?。?/td> 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
Table 6-1. Intel386
TM
DX Instruction Set Clock Count Summary
(Continued)
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
Address
Mode or
Virtual
8086
Mode
INSTRUCTION
FORMAT
Protected
Virtual
Address
Mode
Protected
Virtual
Address
Mode
INTERRUPT INSTRUCTIONS
(Continued)
BOUND:
Via Interrupt or Trap Gate
to Same Privilege Level
Via Interrupt or Trap Gate
to Different Privilege Level
From 80286 Task to 80286 TSS via Task Gate
From 80286 Task to Intel386 DX TSS via Task Gate
From 80268 Task to virt 8086 Mode via Task Gate
From Intel386 DX Task to 80286 TSS via Task Gate
From Intel386 DX Task to Intel386 DX TSS via Task Gate
From 80368 Task to virt 8086 Mode via Task Gate
From virt 8086 Mode to 80286 TSS via Task Gate
From virt 8086 Mode to Intel386 DX TSS via Task Gate
From virt 8086 md to priv level 0 via Trap Gate or Interrupt Gate
59
g, j, k, r
99
254
284
231
264
294
243
264
294
119
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r
g, j, k, r,
g, j, k, r
g, j, k, r
INTERRUPT RETURN
IRET
e
Interrupt Return
1 1 0 0 1 1 1 1
22
g, h, j, k, r
Protected Mode Only (IRET)
To the Same Privilege Level (within task)
To Different Privilege Level (within task)
From 80286 Task to 80286 TSS
From 80286 Task to Intel386 DX TSS
From 80286 Task to Virtual 8086 Task
From 80286 Task to Virtual 8086 Mode (within task)
From Intel386 DX Task to 80286 TSS
From Intel386 DX Task to Intel386 DX TSS
From Intel386 DX Task to Virtual 8086 Task
From Intel386 DX Task to Virtual 8086 Mode (within task)
38
82
232
265
213
60
271
275
223
60
g, h, j, k, r
g, h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
h, j, k, r
PROCESSOR CONTROL
HLT
e
HALT
1 1 1 1 0 1 0 0
5
5
l
MOV
e
Move to and From Control/Debug/Test Registers
CR0/CR2/CR3 from register
0 0 0 0 1 1 1 1
0 0 1 0 0 0 1 0
1 1 eee reg
11/4/5
11/4/5
l
Register From CR0–3
0 0 0 0 1 1 1 1
0 0 1 0 0 0 0 0
1 1 eee reg
6
6
l
DR0–3 From Register
0 0 0 0 1 1 1 1
0 0 1 0 0 0 1 1
1 1 eee reg
22
22
l
DR6–7 From Register
0 0 0 0 1 1 1 1
0 0 1 0 0 0 1 1
1 1 eee reg
16
16
l
Register from DR6–7
0 0 0 0 1 1 1 1
0 0 1 0 0 0 0 1
1 1 eee reg
14
14
l
Register from DR0–3
0 0 0 0 1 1 1 1
0 0 1 0 0 0 0 1
1 1 eee reg
22
22
l
TR6–7 from Register
0 0 0 0 1 1 1 1
0 0 1 0 0 1 1 0
1 1 eee reg
12
12
l
Register from TR6–7
0 0 0 0 1 1 1 1
0 0 1 0 0 1 0 0
1 1 eee reg
12
12
l
NOP
e
No Operation
1 0 0 1 0 0 0 0
3
3
WAIT
e
Wait until BUSY
Y
pin is negated
1 0 0 1 1 0 1 1
7
7
107
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