參數(shù)資料
型號: intel386 DX
廠商: Intel Corp.
英文描述: 32-Bit CHMOS Microprocessor With Integrated Memory Management(32位CHMOS 微處理器帶集成存儲管理)
中文描述: 32位CHMOS微處理器集成內(nèi)存管理(32位CHMOS微處理器帶集成存儲管理)
文件頁數(shù): 108/139頁
文件大小: 1587K
代理商: INTEL386 DX
Intel386
TM
DX MICROPROCESSOR
Table 6-1. Intel386
TM
DX Instruction Set Clock Count Summary
(Continued)
CLOCK COUNT
NOTES
Real
Address
Mode or
Virtual
8086
Mode
Real
Address
Mode or
Virtual
8086
Mode
INSTRUCTION
FORMAT
Protected
Virtual
Address
Mode
Protected
Virtual
Address
Mode
PROCESSOR EXTENSION INSTRUCTIONS
Processor Extension Escape
1 1 0 1 1 T T T
mod L L L
r/m
See
80287/80Intel387
data sheets for
clock counts
h
TTT and LLL bits are opcode
information for coprocessor.
PREFIX BYTES
Address Size Prefix
0 1 1 0 0 1 1 1
0
0
LOCK
e
Bus Lock Prefix
1 1 1 1 0 0 0 0
0
0
m
Operand Size Prefix
0 1 1 0 0 1 1 0
0
0
Segment Override Prefix
CS:
0 0 1 0 1 1 1 0
0
0
DS:
0 0 1 1 1 1 1 0
0
0
ES:
0 0 1 0 0 1 1 0
0
0
FS:
0 1 1 0 0 1 0 0
0
0
GS:
0 1 1 0 0 1 0 1
0
0
SS:
0 0 1 1 0 1 1 0
0
0
PROTECTION CONTROL
ARPL
e
Adjust Requested Privilege Level
From Register/Memory
0 1 1 0 0 0 1 1
mod reg
r/m
N/A
20/21
a
h
LAR
e
Load Access Rights
From Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 1 0
mod reg
r/m
N/A
15/16
a
g, h, j, p
LGDT
e
Load Global Descriptor
Table Register
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1
mod 0 1 0
r/m
11
11
b, c
h, l
LIDT
e
Load Interrupt Descriptor
Table Register
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1
mod 0 1 1
r/m
11
11
b, c
h, l
LLDT
e
Load Local Descriptor
Table Register to
Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
mod 0 1 0
r/m
N/A
20/24
a
g, h, j, l
LMSW
e
Load Machine Status Word
From Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1
mod 1 1 0
r/m
11/14
11/14
b, c
h, l
LSL
e
Load Segment Limit
From Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 1 1
mod reg
r/m
Byte-Granular Limit
Page-Granular Limit
N/A
N/A
21/22
25/26
a
a
g, h, j, p
g, h, j, p
LTR
e
Load Task Register
From Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
mod 0 1 1
r/m
N/A
23/27
a
g, h, j, l
SGDT
e
Store Global Descriptor
Table Register
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1
mod 0 0 0
r/m
9
9
b, c
h
SIDT
e
Store Interrupt Descriptor
Table Register
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 1
mod 0 0 1
r/m
9
9
b, c
h
SLDT
e
Store Local Descriptor Table Register
To Register/Memory
0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0
mod 0 0 0
r/m
N/A
2/2
a
h
108
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